Patents Assigned to STMicroelectronics (Crolles 2)
  • High-sensitivity electronic detector
    Patent number: 10074649
    Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Monfray, Gaspard Hiblot
  • System for identifying a 3D chip
    Patent number: 10075694
    Abstract: A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • System for converting thermal energy into electrical power
    Patent number: 10075102
    Abstract: A system for converting thermal energy into electrical power includes a temperature-sensitive element held in a frame by its two ends between a heat source and a cold source producing a thermal gradient. A piezoelectric element is positioned between the frame and at least one end of the temperature-sensitive element. The temperature-sensitive element is configured to deform cyclically between two states under the action of the thermal gradient. With each cyclic deformation, a stress is applied to the piezoelectric element via the one end.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Arthur Arnaud, Jihane Boughaleb, Stephane Monfray, Thomas Skotnicki
  • Integrated circuit including an active device for confinement of a light flux defined by trenches having a tiered sidewall
    Patent number: 10073219
    Abstract: An integrated circuit includes an active device for confinement of a light flux that is formed in a semiconducting substrate. A confinement rib is separated from two doped zones by two trenches. Each doped zone includes a contacting zone on an upper face. Each trench widens from a bottom wall towards the upper face of the corresponding doped zone. The widening trenches present a sidewall having a tiered profile between the trench and the doped zone. An opposite sidewall presents a straight profile.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Charles Baudot
  • METHOD OF MANUFACTURING A MEMORY DEVICE
    Publication number: 20180254414
    Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28). The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
    Type: Application
    Filed: January 23, 2018
    Publication date: September 6, 2018
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sophie BERNASCONI, Christelle Charpin-Nicolle, Aomar Halimaoui
  • INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
    Publication number: 20180247874
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Application
    Filed: October 3, 2017
    Publication date: August 30, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • OPTICAL COUPLING DEVICE WITH A WIDE BANDWIDTH AND REDUCED POWER LOSSES
    Publication number: 20180239088
    Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.
    Type: Application
    Filed: August 31, 2017
    Publication date: August 23, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot, Florian Domengie
  • INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180233511
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Application
    Filed: April 17, 2018
    Publication date: August 16, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
  • Method and device for testing a chain of flip-flops
    Patent number: 10048317
    Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Clerc, Gilles Gasiot
  • Method and circuit for integrated circuit body biasing
    Patent number: 10050037
    Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 14, 2018
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Florian Cacho, Vincent Huard
  • Image sensor
    Patent number: 10043837
    Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 7, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Philippe Are
  • Electro-optic device with multiple photonic layers and related methods
    Patent number: 10042115
    Abstract: An electro-optic device may include a substrate layer, and a first photonic layer over the substrate layer and having a first photonic device. The electro-optic device may include a second photonic layer over the first photonic layer and having a second photonic device. The electro-optic device may include a dielectric layer over the second photonic layer, and a first electrically conductive via extending through the dielectric layer and the second photonic layer to couple to the first photonic device, and a second electrically conductive via extending through the dielectric layer and coupling to the second photonic device. The electro-optic device may include a third electrically conductive via extending through the substrate layer, the second photonic layer, and the first photonic layer to couple to the substrate layer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: August 7, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Frédéric Boeuf, Charles Baudot
  • CONNECTING BAR
    Publication number: 20180211915
    Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
    Type: Application
    Filed: September 11, 2017
    Publication date: July 26, 2018
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Delia Ristoiu
  • All-around gate field-effect transistor
    Patent number: 10026821
    Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 17, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic Gaben
  • PNP-TYPE BIPOLAR TRANSISTOR MANUFACTURING METHOD
    Publication number: 20180197781
    Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Gregory Avenier
  • Thermal energy harvesting device
    Patent number: 10020758
    Abstract: A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure. A fluid at more than 90% in the liquid state fills the first and second enclosures. A first portion of the first enclosure is in contact with a hot source of a temperature higher than the evaporation temperature of the fluid. A second portion of the first enclosure located between the first portion and the resiliently deformable closed enclosure is in contact with a cold source at a temperature lower than the condensation temperature of the fluid. An electromechanical transducer is coupled to a deformable membrane of the resiliently deformable closed enclosure.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 10, 2018
    Assignees: STMicroelectronics (Crolles 2) SAS, SOCPRA Sciences et Génie S.E.C.
    Inventors: Gholamreza Mirshekari, Etienne Leveille, Luc Guy Frechette, Stephane Monfray, Thomas Skotnicki
  • Three-dimensional integrated photonic structure with improved optical properties
    Patent number: 10012792
    Abstract: An integrated electronic device includes a substrate having an opening extending therethrough. The substrate includes an interconnection network, and connections coupled to the interconnection network. The connections are to be fixed on a printed circuit board. An integrated photonic module is electrically connected to the substrate, with a portion of the integrated photonic module in front of or overlapping the opening of the substrate. An integrated electronic module is electrically connected to the photonic module, and extends at least partly into the opening of the substrate. The electronic module and the substrate may be electrically connected onto the same face of the photonic module.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 3, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Francois Carpentier, Patrick Lemaitre, Mickael Fourel
  • Method of manufacturing a nanostructured spectral filter
    Patent number: 10014337
    Abstract: A spectral filter is manufactured using a process wherein a first rectangular bar is formed within a first layer made of a first material, said first rectangular bar being made of a second material having a different optical index. The process further includes, in a second layer over the first layer, a second rectangular bar made of the second material. The second rectangular bar is positioned in contact with the first rectangular bar. The second layer is also made of the first material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 3, 2018
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Romain Girard Desprolet, Michel Marty, Salim Boutami, Sandrine Lhostis
  • Electronic chip manufacturing method
    Patent number: 10014308
    Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 3, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Zoll, Philippe Garnier
  • Laser device and process for fabricating such a laser device
    Patent number: 10014660
    Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 3, 2018
    Assignees: Commisariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Thomas Ferrotti, Badhise Ben Bakir, Alain Chantre, Sebastien Cremer, Helene Duprez