Patents Assigned to STMicroelectronics (Crolles 2)
  • Single photon avalanche gate sensor device
    Patent number: 10193009
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 29, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • ELECTRONIC IMAGE CAPTURE DEVICE
    Publication number: 20190027523
    Abstract: An electronic image capture device includes a first portion and a second portion. The first portion is formed by a substrate wafer provided on one side with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The second portion includes a pixel wafer capable of generating electrical signals under the effect of light, a substrate wafer mounted to the pixel wafer and provided with electronic circuits and a dielectric layer with a network of electrical connections and external electrical contacts on an outer surface. The outer surfaces and external electrical contacts are bonded to each other so as to mount the first portion to the second portion. A connection pad extends through a hole in the pixel wafer to make electrical connection to the network of electrical connections of the second portion.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Cyclic epitaxy process to form air gap isolation for a bipolar transistor
    Patent number: 10186605
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Fabien Deprat, Yves Campidelli
  • Integrated circuit chip reinforced against front side deprocessing attacks
    Patent number: 10186491
    Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 22, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Sébastien Petitdidier, Mathieu Lisart
  • Heat pipe and method of manufacturing the same
    Patent number: 10186474
    Abstract: A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed radially extending around a central axis of the opening; arranging in the recesses separate ring-shaped strips made of a material catalyzing the growth of carbon nanotubes; and growing carbon nanotubes in the opening from said ring-shaped strips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 22, 2019
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pascal Ancey, Simon Gousseau, Olga Kokshagina
  • OPTICAL COUPLING DEVICE WITH A WIDE BANDWIDTH AND REDUCED POWER LOSSES
    Publication number: 20190018191
    Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.
    Type: Application
    Filed: September 17, 2018
    Publication date: January 17, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot, Florian Domengie
  • Opto electrical test measurement system for integrated photonic devices and circuits
    Patent number: 10180373
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 15, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
  • Image sensor with vertical electrodes
    Patent number: 10170513
    Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.
    Type: Grant
    Filed: September 23, 2017
    Date of Patent: January 1, 2019
    Assignees: Commissariat à l'Energie Atomique et aux Energies, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Yvon Cazaux, François Roy, Marie Guillon, Arnaud Laflaquiere
  • PHASE-CHANGE MEMORY CELL
    Publication number: 20180374898
    Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Gourvest, Yannick Le Friec, Laurent Favennec
  • ION SENSITIVE FIELD EFFECT TRANSISTOR (ISFET) HAVING HIGHER SENSITIVITY IN RESPONSE TO DYNAMIC BIASING
    Publication number: 20180372679
    Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Getenet Tesega Ayele, Stephane Monfray
  • METHOD OF MANUFACTURING A SPAD CELL
    Publication number: 20180374983
    Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Dominique GOLANSKI, Jean JIMENEZ, Didier DUTARTRE, Olivier GONNARD
  • Time-of-flight detection pixel
    Patent number: 10162048
    Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 25, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Boris Rodrigues, Marie Guillon, Yvon Cazaux, Benoit Giffard
  • Method for characterization of photonic devices, and associated device
    Patent number: 10161830
    Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 25, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Patrick Le Maitre, Jean-Francois Carpentier
  • THERMO-ELECTRIC GENERATOR
    Publication number: 20180358535
    Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 13, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Dubois, Jean-Francois Robillard, Stephane Monfray, Thomas Skotnicki
  • Image sensor device with first and second source followers and related methods
    Patent number: 10153318
    Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: François Roy, Frédéric Lalanne, Pierre Emmanuel Marie Malinge
  • Back-side illuminated pixel
    Patent number: 10153312
    Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 11, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: François Roy, Helene Wehbe-Alause, Olivier Noblanc
  • Image sensor chip
    Patent number: 10147748
    Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 4, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Francois Guyader
  • Method for making photonic chip with multi-thickness electro-optic devices and related devices
    Patent number: 10139563
    Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 27, 2018
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Alain Chantre, Sébastien Cremer
  • DEVICE FOR MEASURING DOSES OF IONIZING PARTICLES
    Publication number: 20180335526
    Abstract: Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 22, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, Centre National De La Recherche Scientifique
    Inventors: Martin COCHET, Dimitri SOUSSAN, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE
  • METHOD FOR FORMING A PLANARIZATION STRUCTURE
    Publication number: 20180330961
    Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 15, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic GABEN