Patents Assigned to STMicroelectronics (Crolles 2)
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Publication number: 20170336560Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.Type: ApplicationFiled: December 13, 2016Publication date: November 23, 2017Applicant: STMicroelectronics (Crolles 2) SASInventors: Frederic Boeuf, Charles Baudot
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Patent number: 9825080Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.Type: GrantFiled: December 17, 2015Date of Patent: November 21, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: Nayera Ahmed, François Roy
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Patent number: 9825076Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.Type: GrantFiled: April 11, 2016Date of Patent: November 21, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: François Roy, Helene Wehbe-Alause, Olivier Noblanc
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Patent number: 9810823Abstract: An infrared high-pass plasmonic filter includes a copper layer interposed between two layers of a dielectric material. An array of patterned openings extend through the copper layer and are filled with the dielectric material. Each patterned opening is in the shape of a greek cross, with the arms of adjacent patterns being collinear. A ratio of the width to the length of each arm is in the range from 0.3 to 0.6, and the distance separating the opposite ends of arms of adjacent patterns is shorter than 10 nm.Type: GrantFiled: November 21, 2016Date of Patent: November 7, 2017Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Romain Girard Desprolet, Sandrine Lhostis, Salim Boutami
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Publication number: 20170317106Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.Type: ApplicationFiled: November 28, 2016Publication date: November 2, 2017Applicants: STMicroelectronics (Rousset 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Franck Arnaud, Gregory Bidal, Dominique Golanski, Emmanuel Richard
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Publication number: 20170307687Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.Type: ApplicationFiled: April 17, 2017Publication date: October 26, 2017Applicant: STMicroelectronics (Crolles 2) SASInventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
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Publication number: 20170299651Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.Type: ApplicationFiled: December 14, 2016Publication date: October 19, 2017Applicant: STMicroelectronics (Crolles 2) SASInventor: Sylvain Clerc
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Patent number: 9791346Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.Type: GrantFiled: April 20, 2016Date of Patent: October 17, 2017Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Jean-Francois Carpentier, Patrick Lemaitre, Jean-Robert Manouvrier, Charles Baudot, Bertrand Borot
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Patent number: 9793321Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.Type: GrantFiled: December 15, 2015Date of Patent: October 17, 2017Assignees: STMicroelectronics (Crolles 2) SAS, STMicrolectronics (Rousset) SASInventors: Philippe Boivin, Simon Jeannot
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Patent number: 9793312Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.Type: GrantFiled: August 5, 2016Date of Patent: October 17, 2017Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 9793396Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.Type: GrantFiled: May 31, 2016Date of Patent: October 17, 2017Assignees: STMicroelectronics, Inc., STMicroelectronics (Crolles 2) SASInventors: Qing Liu, Thomas Skotnicki
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Publication number: 20170294379Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
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Patent number: 9786755Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.Type: GrantFiled: November 2, 2015Date of Patent: October 10, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: Dominique Golanski, Gregory Bidal, Simon Jeannot
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Publication number: 20170288781Abstract: An optical modulator includes an optical waveguide including at least a first PN junction phase shifter and a second PN junction phase shifter. A driver circuit drives operation of the first and second PN junction phase shifters in response to a pulse amplitude modulated (PAM) analog signal having 2n levels. The PAM analog signal is generated by a digital to analog converter that receives an n-bit input signal. In an implementation, the optical waveguide and PN junction phase shifters are formed on a first integrated circuit chip and the driver circuit is formed on a second integrated circuit chip that is stacked on and electrically connected to the first integrated circuit chip.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Jean-Francois Carpentier, Patrick Lemaitre, Jean-Robert Manouvrier, Denis Pache, Stephane Le Tual
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Publication number: 20170287806Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.Type: ApplicationFiled: March 7, 2017Publication date: October 5, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
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Patent number: 9778415Abstract: An arrayed waveguide grating multiplexer/demultiplexer includes an array of optical waveguides ordered in sequence from a shortest waveguide up to a longest waveguide, and identical phase shifters configured to be controlled by a same control signal. Each phase shifter increases/decreases an optical path of an optical waveguide by the same quantity based on the control control signal.Type: GrantFiled: November 15, 2016Date of Patent: October 3, 2017Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS S.R.L.Inventors: Antonio Fincato, Charles Baudot
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Patent number: 9780015Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.Type: GrantFiled: July 7, 2016Date of Patent: October 3, 2017Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Pierre Bar, Alisee Taluy, Olga Kokshagina
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Publication number: 20170278892Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.Type: ApplicationFiled: August 5, 2016Publication date: September 28, 2017Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Publication number: 20170271470Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.Type: ApplicationFiled: March 21, 2017Publication date: September 21, 2017Applicants: Commissariat a I'energie atomique et aux energies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Cyrille LE ROYER, Frederic Boeuf, Laurent Grenouillet, Louis Hutin, Yves Morand
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Publication number: 20170271325Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.Type: ApplicationFiled: March 9, 2017Publication date: September 21, 2017Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
