Patents Assigned to STMicroelectronics (Crolles 2)
  • Electrode for a metal-insulator-metal structure, capacitor of metal-insulator-metal type, and method for fabricating one such electrode and one such capacitor
    Patent number: 10319806
    Abstract: The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer. The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide. The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide. The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 11, 2019
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Guillaume Rodriguez, Aomar Halimaoui, Laurent Ortiz
  • CRACK SENSOR FOR SENSING CRACKS IN A SOLDER PAD, AND METHOD FOR PRODUCTION QUALITY CONTROL
    Publication number: 20190172795
    Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 6, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Eric SABOURET, Krysten ROCHEREAU, Olivier HINSINGER, Flore PERSIN-CRELEROT
  • Method of manufacturing bistable strips having different curvatures
    Patent number: 10312431
    Abstract: A method of manufacturing bistable strips having different curvatures, each strip including a plurality of portion of layers of materials, wherein at least one specific layer portion is deposited by a plasma spraying method in conditions different for each of the strips.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 4, 2019
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Emilie Trioux, Pascal Ancey, Stephane Monfray, Thomas Skotnicki, Skandar Basrour, Paul Muralt
  • PHOTONIC INTERCONNECT SWITCHES AND NETWORK INTEGRATED INTO AN OPTOELECTRONIC CHIP
    Publication number: 20190162906
    Abstract: An elementary photonic interconnect switch is integrated into an optoelectronic chip and includes four simple photonic interconnect switches. Each simple photonic interconnect switch has two optical waveguides that cross and are linked by a ring resonator having one ring. A basic photonic interconnect switch, a complex photonic interconnect switch and/or a photonic interconnect network are integrated into an optoelectronic chip and including at least two elementary photonic interconnect switches.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 30, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas MICHIT, Patrick LE MAITRE
  • Back-side illuminated image sensor
    Patent number: 10304893
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Method for estimating an operating profile of an integrated circuit of a system-on-a-chip, and corresponding system-on-a-chip
    Patent number: 10302693
    Abstract: A system-on-a-chip includes an integrated circuit and an estimation circuit. The estimation circuit operates to acquire at least one physical parameter representative of the use of the integrated circuit and determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter. A margin of use of the integrated circuit is then calculated by comparing the instantaneous state of aging with a presumed state of aging.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • Connecting bar
    Patent number: 10304775
    Abstract: A connecting bar electrically connects separate circuit zones of an integrated circuit. The connecting bar is formed by a main portion that is a conductive strip extending above separate circuit zones to be interconnected. The conductive strip is separated from the integrated circuit by a dielectric except at the circuit zones to be interconnected. The connecting bar further includes secondary portions that are conductive pads passing through the dielectric in a vertical direction from the circuit zone to the conductive strip.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 28, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Delia Ristoiu
  • Device for converting thermal energy into electrical energy
    Patent number: 10298151
    Abstract: A power conversion device includes an enclosure containing one or more drops of a liquid. A capacitive electret transducer is coupled to the enclosure. In response to applied heat at a heating surface, the liquid vaporizes and then condenses on a flexible membrane of the capacitive electret transducer. The flexible membrane is displaced in response to the vaporization-condensation and the capacitive electret transducer generates an output current.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 21, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Stephane Monfray, Christophe Maitre, Olga Kokshagina, Thomas Skotnicki, Ulrich Soupremanien
  • HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190148531
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALIDATING PROPER OPERATION OF A STATIC RANDOM ACCESS MEMORY (SRAM)
    Publication number: 20190146868
    Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
    Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
  • Junction region between two waveguides and associated method of production
    Patent number: 10288806
    Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region the includes a bulge region.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Charles Baudot
  • CHIP CONTAINING AN ONBOARD NON-VOLATILE MEMORY COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20190140176
    Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH COUNTER-DOPED COLLECTOR REGION AND METHOD OF MAKING SAME
    Publication number: 20190140072
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier
  • MEMORY CELL COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20190140175
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 9, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier HINSINGER
  • Resistive memory cell having a compact structure
    Patent number: 10283563
    Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 7, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Simon Jeannot
  • Low-noise high dynamic range image sensor
    Patent number: 10284798
    Abstract: An image sensor includes a plurality of pixels each including a first photodiode linked to a capacitive readout node by a first transistor, and a second photodiode linked to a first capacitive storage node by a second transistor, the first capacitive node being linked to the readout node by a third transistor, and the readout node being linked to a node for applying a reset potential by a fourth transistor.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: May 7, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Didier Herault, Pierre Malinge
  • Testing circuit of a longtime-constant circuit stage and corresponding testing method
    Patent number: 10281512
    Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 7, 2019
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
    Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
  • Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit
    Patent number: 10283588
    Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Emmanuel Perrin
  • MEMORY CELL COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20190131521
    Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10?5 ?·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 2, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre MORIN, Didier DUTARTRE
  • MEMORY CELL COMPRISING A PHASE-CHANGE MATERIAL
    Publication number: 20190131520
    Abstract: A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 2, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre MORIN, Franck ARNAUD, Didier DUTARTRE