Abstract: An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are formed to extend from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate.

Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.

Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract: An image sensor including a control circuit and a plurality of pixels, each pixel including: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area; first and second insulated vertical electrodes electrically connected to each other, opposite each other, and delimiting the storage area, the first electrode extending between the storage area and the photosensitive area, the second electrode including a bent extension opposite a first end of the first electrode, the storage area emerging onto the photosensitive area on the side of the first end, the control circuit being capable of applying a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block said transfer.

Abstract: A spectral filter includes an assembly of filtering cells. Each cell has a same nanostructured pattern and a preferential direction of the pattern. This preferential direction is, for each cell, oriented approximately radially with respect to a single point of the spectral filter. Alternatively, this preferential direction is, for each cell, oriented approximately ortho-radially with respect to the single point of the spectral filter. The single point may be a center point. Alternatively, the single point may correspond to an optical axis of a lens element associated with the spectral filter.

Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.

Abstract: A system for converting thermal energy into electrical power includes a temperature-sensitive element held in a frame by its two ends between a heat source and a cold source producing a thermal gradient. A piezoelectric element is positioned between the frame and at least one end of the temperature-sensitive element. The temperature-sensitive element is configured to deform cyclically between two states under the action of the thermal gradient. With each cyclic deformation, a stress is applied to the piezoelectric element via the one end.

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.

Abstract: A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.

Abstract: A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.

Abstract: An integrated circuit chip cooling device includes a network of micropipes. A first pipe portion and a second pipe portion of the network are connected by at least one valve. The valve is formed of a bilayer strip. In response to change in temperature, the shape of the bilayer strip changes to move the valve from a substantially closed position to an open position. In one configuration, the change is irreversible. In another configuration, the change is reversible in response to an opposite change in temperature.

Abstract: A spectral filter is manufactured using a process wherein a first rectangular bar is formed within a first layer made of a first material, said first rectangular bar being made of a second material having a different optical index. The process further includes, in a second layer over the first layer, a second rectangular bar made of the second material. The second rectangular bar is positioned in contact with the first rectangular bar. The second layer is also made of the first material.

Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s) d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.