Abstract: An electronic device includes a base substrate having a mounting face. An electronic chip is fastened onto the mounting face of the base substrate. A transparent encapsulation structure is bonded onto the base substrate. The transparent encapsulation structure includes a housing with an internal cavity defining a chamber housing the electronic chip. The encapsulation structure has an external face that supports a light-filtering optical wafer located facing an optical element of the electronic chip. An opaque cover covers the transparent encapsulation structure and includes a local opening facing the light-filtering optical wafer.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

Abstract: A pressure sensor has a body having a first chamber and a second chamber hermetically separated from the first chamber; a first detection structure which is arranged in the first chamber, has a first deformable element and a first buried cavity within the first detection structure, wherein the first deformable element is configured to undergo a deformation as a function of a pressure difference between the first chamber and the first buried cavity. The sensor also has a second detection structure which is arranged in the second chamber, has a second deformable element and a second buried cavity within the second detection structure, wherein the second deformable element is configured to undergo a deformation as a function of a pressure difference between the second chamber and the second buried cavity.

Abstract: The present description concerns a method of verification, implemented by an electronic device, of a matrix used for the implementation of a data cipher algorithm comprising, for the generation of the matrix, the use of a first function and of a second function, the verification method comprising a verification using a final portion of the output data of the first function.

Abstract: An avalanche photodiode includes first semiconductor region of a first conductivity type in a semiconductor substrate and a second semiconductor region of a second conductivity type in the semiconductor substrate which forming a PN junction to be reverse-biased. A third semiconductor region of the second conductivity type in the semiconductor substrate is positioned such that the second region is closer to the first region than the third region. A fourth semiconductor region of the second conductivity type in a semiconductor substrate is in contact with the second and third regions. A dopant concentration of the fourth region is less than dopant concentrations of the second and third regions. The fourth region is arranged to at least partially surround the second region, and the third region is arranged to at least partially surround the fourth region.

Abstract: Provided is voltage regulator circuit including an input node for receiving an input supply voltage, an output node for producing an output regulated voltage, and a switchable pass element arranged between the input and output nodes. A comparator circuit compares the output regulated voltage to a dynamic threshold to produce a control signal to control the switchable pass element. The control signal being asserted results in the switchable pass element being turned on, and vice-versa. A threshold selection and shaping circuit shapes the output regulated voltage or the dynamic threshold so that: (i) in response to assertion of the control signal, the difference between the dynamic threshold and the output regulated voltage is abruptly increased and subsequently gradually decreased towards a target static value, and (ii) in response to de-assertion of the control signal, the difference is abruptly increased and subsequently gradually decreased towards a target static value.

Abstract: A power-management system includes a power transistor coupled between a power supply and load, a driver circuit driving the power transistor in response to an input signal, and an error amplifier generating a control signal that modifies operation of the driver circuit based on a comparison between a selected reference voltage and a drain-to-source voltage of the power transistor. A multiplexer provides the selected reference voltage to the error amplifier and passes one of a plurality of different reference voltages as the selected reference voltage based upon first and second selection signals. A first selection circuit charges a first capacitor in response to the input signal and generates the first selection signal based on a first voltage across the first capacitor. A second selection circuit charges a second capacitor in response to the input signal and generates the second selection signal based on a second voltage across the second capacitor.

Abstract: A thermoelectric generator includes a thermoelectric converter and a thermal coupling structure, configured to thermally couple the thermoelectric converter to a first body at a first temperature and to a second body at a second temperature, lower than the first temperature. The thermoelectric converter includes a support body, having a structural layer and a thermal insulation layer, and a plurality of thermopiles arranged on the thermal insulation layer and thermally coupled to the thermal coupling structure. The thermal insulation layer has a thickness such as to thermally insulate the thermopiles from the structural layer and the support body is continuous and without cavities between the thermopiles and a face of the structural layer opposite to the thermopiles.

Abstract: The present disclosure is directed to transducer assemblies or device in which one or more buried cavities are present within a substrate and define or form one or more membranes along a surface of the substrate. One or more piezoelectric actuators are formed on the one or more membranes and the one or more piezoelectric actuators drive the membranes at an operating frequency with an operating bandwidth of the transducer assemblies. Each of the one or more membranes is anchored at respective portions to a main body portion of the substrate to provide robust and strong anchoring of each of the one or more membranes to push unwanted flexure modes outside the operating bandwidth of the transducer assemblies.

Abstract: An electronic device includes a power supply terminal, a voltage regulator connected to the power supply terminal, an electronic module connected to the voltage regulator, and a compensation circuit configured to receive an auxiliary current generated by the voltage regulator and being equal to a first fraction of the electronic module current. The compensation circuit includes a current source configured to supply a source current to a cold point, and a compensation stage connected to the power supply terminal and being traversed by an intermediate current equal to a difference between the source current and the auxiliary current and by a complementary current equal to the intermediate current multiplied by an inverse multiplication factor of the first fraction.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: Wettable metalization multilayer formed by an adhesion layer, containing titanium; a barrier layer, containing nickel; and a sintering layer, containing silver. A portion of the sintering layer, facing the barrier layer, contains atoms of a metal material chosen between aluminum and tin. A portion of the barrier layer facing the sintering layer may contain atoms of the metal material. The sintering layer is obtained depositing by PVD and spinning a metal material layer and then a silver layer, causing the diffusion of the atoms of the metal material in the silver layer.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

Abstract: A semiconductor die is arranged at a die mounting region at a first surface of a die pad in a substrate. The die pad has a second surface opposite the first surface. Laser beam energy is applied to the second surface of the die pad to form in the second surface of the die pad a recessed peripheral portion surrounding a central portion opposite the die mounting region at the first surface. An encapsulation of electrically insulating material is molded onto the substrate. During molding, the electrically insulating material covers the recessed peripheral portion and leakage of the electrically insulating material over the central portion is countered in response to the peripheral portion of the second surface of the die pad being recessed.

Abstract: A system includes a module formed by a first supporting portion, a second supporting portion, a first die carrying a first reflector and housed in the first supporting portion, and a second die carrying a second reflector and housed in the second supporting portion. The first and second supporting portions are spaced apart to define a gap therebetween. The second supporting portion includes an input hole defined therein to receive an incoming beam and direct it toward the first reflector. The first supporting portion includes an output hole defined therein to allow passage of an outgoing beam reflected by the second reflector. The first and second reflectors are configured to sequentially reflect the incoming beam to generate the outgoing beam.

Abstract: Various embodiments provide an optical lens that includes wafer level diffractive microstructures. In one embodiment, the optical lens includes a substrate, a microstructure layer having a first refractive index, and a protective layer having a second refractive index that is different from the first refractive index. The microstructure layer is formed on the substrate and includes a plurality of diffractive microstructures. The protective layer is formed on the diffractive microstructures. The protective layer provides a cleanable surface and encapsulates the diffractive microstructures to prevent damage and contamination to the diffractive microstructures. In another embodiment, the optical lens includes a substrate and an anti-reflective layer. The anti-reflective layer is formed on the substrate and includes a plurality of diffractive microstructures.

Abstract: An embodiment pulse generator circuit is configured to apply a current pulse to two output terminals. The pulse generator circuit comprises an LC resonant circuit comprising an inductance and a capacitance connected in series between a first node and a negative input terminal. The pulse generator circuit comprises a charge circuit configured to charge the capacitance via a supply voltage, a first electronic switch configured to selectively short-circuit the two output terminals, a second electronic switch configured to selectively connect the two output terminals in parallel with the LC resonant circuit, and a control circuit configured to drive the first and the second electronic switch.