Patents Assigned to STMicroelectronics (Grenoble 2) SAS
  • Patent number: 12279350
    Abstract: A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates thep sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.
    Type: Grant
    Filed: May 23, 2024
    Date of Patent: April 15, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Maria Francesca Seminara, Salvatore Rosario Musumeci
  • Patent number: 12278155
    Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 15, 2025
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Younes Boutaleb, Fabien Quercia, Asma Hajji, Ouafa Hajji
  • Publication number: 20250120106
    Abstract: A method of making a bipolar transistor includes: forming a first collector part of a first conductivity type in a semiconductor layer; forming a first insulating region made of a first insulating material on the first collector part; forming a conduction layer intended to form a first doped base part of the second conductivity type on the first insulating region; forming an opening having a first width in the conduction layer that emerges onto the first insulating region; forming an insulating layer on the conduction layer and in the opening; forming a cavity in the insulating layer and in the first insulating region that emerges onto a portion of the first collector part through the opening, the cavity having at the level of the opening a second width smaller than the first width; and forming a second collector part in the cavity on the portion of the first collector part.
    Type: Application
    Filed: October 3, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Arnaud RIVAL, Alexis GAUTHIER, Edoardo BREZZA, Pascal CHEVALIER
  • Publication number: 20250120326
    Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Philippe BOIVIN
  • Publication number: 20250118703
    Abstract: A semiconductor chip is covered by a non-LDS encapsulation material (i.e., encapsulation material not including LDS-activatable additives). One or more first pathways are opened towards the semiconductor chip through the non-LDS encapsulation material. LDS encapsulation material (i.e., encapsulation material including LDS-activatable additives) is molded over the non-LDS encapsulation material to fill the first pathways. One or more second pathways, aligned with the first pathways, are opened towards the semiconductor chip through the LDS encapsulation material. The second pathways have an inner lining of LDS encapsulation material. Electrical coupling formations for the semiconductor chip are provided via laser direct structuring processing of the LDS encapsulation material including the inner lining in the second pathways.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Claudio ZAFFERONI, Antonio BELLIZZI, Alessandro MELLINA GOTTARDO
  • Publication number: 20250119061
    Abstract: A DC-DC converter circuit includes a switching stage with first and second switches, and a control circuit coupled to the switching stage. The control circuit detects a threshold for changing between a synchronous operation mode and an asynchronous operation mode, synchronizes the detected threshold with a beginning of a new switching cycle, applies feed-forward compensation at the beginning of an ON-time period to vary a duty cycle, and generates drive signals to control the switching stage.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro BERTOLINI, Alberto CATTANI, Stefano RAMORINI, Alessandro GASPARINI
  • Publication number: 20250120319
    Abstract: A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Irene MARTINI, Davide ASSANELLI, Paolo FERRARINI, Carlo Luigi PRELINI, Fabio QUAGLIA
  • Publication number: 20250119056
    Abstract: Provided is a power supply control circuit for a power supply, including a PFC converter configured to generate a bus voltage, an electronic converter and an auxiliary power supply configured to generate an auxiliary supply voltage. The PFC converter comprises a PFC control circuit configured to drive the PFC converter to regulate the bus voltage to a requested value. When the output power is greater than the threshold, the power supply control circuit supplies the PFC control circuit with the auxiliary supply voltage. When the output power is smaller than the threshold, the circuit compares the bus voltage to upper and lower thresholds. When the bus voltage is greater than the upper threshold, the circuit inhibits supply of the PFC control circuit with the auxiliary supply voltage. When the bus voltage is smaller than a lower threshold, the circuit supplies the PFC control circuit with the auxiliary supply voltage.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 10, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Fabio CACCIOTTO, Salvatore TORRISI
  • Patent number: 12273030
    Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventor: Stefano Ramorini
  • Patent number: 12272416
    Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Balwinder Singh Soni, Avneep Kumar Goyal
  • Patent number: 12273089
    Abstract: The integrated circuit includes a power amplifier intended to provide a signal in a fundamental frequency band, an antenna, and a matching and filtering network having a first section, a second section, and a third section. The three sections include LC arrangements configured to have an impedance matched to the power amplifier's output in the fundamental frequency band. The LC arrangements of the first section and the second section are configured to have resonant frequencies adapted to attenuate the harmonic frequency bands of the fundamental frequency band.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Guillaume Blamon, Emmanuel Picard, Christophe Boyavalle
  • Patent number: 12270842
    Abstract: In an embodiment method for detecting the phase of an analog signal via a hybrid coupler operating in a power-combiner mode, the hybrid coupler comprises a first input intended to receive the analog signal, a second input intended to receive a reference signal having a reference phase and the same frequency as the analog signal, and two outputs, and is configured to generate, at these two outputs, a first output signal and a second output signal, respectively. The embodiment method comprises measuring peak values of the analog signal, of the reference signal, and of at least one of the first and second output signals, calculating the phase shift between the phase of the analog signal and the reference phase depending on the measured peak values, and determining the phase of the analog signal depending on the calculated phase shift and the reference phase.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 8, 2025
    Assignees: STMicroelectronics France, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE DE BORDEAUX, INSTITUT POLYTECHNIQUE DE BORDEAUX
    Inventors: Vincent Knopik, Jeremie Forest, Eric Kerherve
  • Patent number: 12270990
    Abstract: A microelectromechanical mirror device includes a fixed structure defining a cavity, a tiltable structure elastically suspended above the cavity and carrying a reflecting surface, and having a main extension in a horizontal plane. A first pair of driving arms carry respective piezoelectric material regions that are biased to cause a rotation of the tiltable structure around a first rotation axis parallel to a first horizontal axis of the horizontal plane, and elastically coupled to the tiltable structure. Elastic suspension elements that couple the tiltable structure to the fixed structure at the first rotation axis are stiff with respect to movements out of the horizontal plane and yielding with respect to torsion around the first rotation axis, and further extend between the tiltable structure and the fixed structure. The elastic suspension elements have an asymmetrical arrangement on opposite sides of the tiltable structure along the first rotation axis.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo' Boni, Roberto Carminati, Massimiliano Merli
  • Patent number: 12274003
    Abstract: A device includes comprising first and second printed circuit boards. Walls couple the first and second printed circuit boards to each other and define a first cavity between the first and second printed circuit boards. Electric conductors associated with the walls electrically connect the first and second printed circuit boards. An integrated circuit chip is mounted to a first surface of the first integrated circuit board in the first cavity. The integrated circuit chip is electrically connected to conductive tracks of the first surface of the first printed circuit board. Surface-mounted components are mounted on top of and in contact with conductive tracks of a first surface of the second printed circuit board. The first surfaces of the first and second printed circuit boards are arranged facing towards each other. The first and second printed circuit boards may form rigid components of a flex-rigid type printed circuit board.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Patrick Laurent, Jean-Michel Riviere
  • Patent number: 12273117
    Abstract: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Prashutosh Gupta
  • Patent number: 12271607
    Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: April 8, 2025
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Jawad Benhammadi
  • Publication number: 20250113511
    Abstract: To manufacture a bipolar transistor, a first stack of layers including a first layer made of the material of the base of the bipolar transistor is formed between second and third insulating layers. A first cavity is then formed crossing the first stack in such a way as to reach the substrate. The forming of the first cavity includes an etching of no layer covering the first layer other than the third layer. A first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor are then formed in the first cavity.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 3, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Edoardo BREZZA, Alexis GAUTHIER
  • Publication number: 20250110535
    Abstract: The present disclosure is directed to routine recognition for adjusting the power state of a device. Human activity recognition is performed to detect various activity states, and create a current sequence of activity states. In response to detecting a new activity state, routine comparison is performed in order to compare the current sequence to a past sequence that ended with the user starting to interact with the device. The device is preemptively turned on in response to finding a match.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Lorenzo Francesco GUALNIERA, Stefano Paolo RIVOLTA, Piergiorgio ARRIGONI, Marco BIANCO
  • Publication number: 20250110462
    Abstract: Provided is a multi-channel actuator for driving a low-side device. The actuator includes a controller that receives a first command for driving a low-side device and outputs data representative of the first command. The actuator includes a driving circuit having a plurality of detection and driving stages. The plurality of detection and driving stages are operative to be coupled to a plurality of channels of the low-side device, respectively. The driving circuit receives the data representative of the first command and causes a detection and driving stage of the plurality of detection and driving stages to drive a respective channel of the low-side device in accordance with the first command.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: STMicroelectronics International N.V.
    Inventors: Guozhu FENG, Allan Rio Valentos LAGASCA
  • Publication number: 20250112107
    Abstract: At least one package includes a die including a first surface, a second surface opposite to the first surface, and one or more sidewalls transverse to the first surface and the second surface. The one or more sidewalls extend from the first surface to the second surface. A plurality of separate and distinct heat sinks is on the first surface of the die. Each respective separate and distinct heat sink of the plurality of separate and distinct heat sinks is separate and distinct from adjacent separate and distinct heat sinks of the plurality of separate and distinct heat sinks. A plurality of channels separates each respective heat sink of the plurality of heat sinks from adjacent heat sinks of the plurality of heat sinks. In some packages, an elastic thermally conductive material is present within and fills the plurality of channels.
    Type: Application
    Filed: September 19, 2024
    Publication date: April 3, 2025
    Applicant: STMicroelectronics International N.V.
    Inventor: Roseanne DUCA