Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Abstract: A semiconductor die is arranged at a die mounting region at a first surface of a die pad in a substrate. The die pad has a second surface opposite the first surface. Laser beam energy is applied to the second surface of the die pad to form in the second surface of the die pad a recessed peripheral portion surrounding a central portion opposite the die mounting region at the first surface. An encapsulation of electrically insulating material is molded onto the substrate. During molding, the electrically insulating material covers the recessed peripheral portion and leakage of the electrically insulating material over the central portion is countered in response to the peripheral portion of the second surface of the die pad being recessed.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

Abstract: A system includes a module formed by a first supporting portion, a second supporting portion, a first die carrying a first reflector and housed in the first supporting portion, and a second die carrying a second reflector and housed in the second supporting portion. The first and second supporting portions are spaced apart to define a gap therebetween. The second supporting portion includes an input hole defined therein to receive an incoming beam and direct it toward the first reflector. The first supporting portion includes an output hole defined therein to allow passage of an outgoing beam reflected by the second reflector. The first and second reflectors are configured to sequentially reflect the incoming beam to generate the outgoing beam.

Abstract: Various embodiments provide an optical lens that includes wafer level diffractive microstructures. In one embodiment, the optical lens includes a substrate, a microstructure layer having a first refractive index, and a protective layer having a second refractive index that is different from the first refractive index. The microstructure layer is formed on the substrate and includes a plurality of diffractive microstructures. The protective layer is formed on the diffractive microstructures. The protective layer provides a cleanable surface and encapsulates the diffractive microstructures to prevent damage and contamination to the diffractive microstructures. In another embodiment, the optical lens includes a substrate and an anti-reflective layer. The anti-reflective layer is formed on the substrate and includes a plurality of diffractive microstructures.

Abstract: An embodiment pulse generator circuit is configured to apply a current pulse to two output terminals. The pulse generator circuit comprises an LC resonant circuit comprising an inductance and a capacitance connected in series between a first node and a negative input terminal. The pulse generator circuit comprises a charge circuit configured to charge the capacitance via a supply voltage, a first electronic switch configured to selectively short-circuit the two output terminals, a second electronic switch configured to selectively connect the two output terminals in parallel with the LC resonant circuit, and a control circuit configured to drive the first and the second electronic switch.

Abstract: A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates thep sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A method of making a bipolar transistor includes: forming a first collector part of a first conductivity type in a semiconductor layer; forming a first insulating region made of a first insulating material on the first collector part; forming a conduction layer intended to form a first doped base part of the second conductivity type on the first insulating region; forming an opening having a first width in the conduction layer that emerges onto the first insulating region; forming an insulating layer on the conduction layer and in the opening; forming a cavity in the insulating layer and in the first insulating region that emerges onto a portion of the first collector part through the opening, the cavity having at the level of the opening a second width smaller than the first width; and forming a second collector part in the cavity on the portion of the first collector part.

Abstract: A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.

Abstract: A semiconductor chip is covered by a non-LDS encapsulation material (i.e., encapsulation material not including LDS-activatable additives). One or more first pathways are opened towards the semiconductor chip through the non-LDS encapsulation material. LDS encapsulation material (i.e., encapsulation material including LDS-activatable additives) is molded over the non-LDS encapsulation material to fill the first pathways. One or more second pathways, aligned with the first pathways, are opened towards the semiconductor chip through the LDS encapsulation material. The second pathways have an inner lining of LDS encapsulation material. Electrical coupling formations for the semiconductor chip are provided via laser direct structuring processing of the LDS encapsulation material including the inner lining in the second pathways.

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: A DC-DC converter circuit includes a switching stage with first and second switches, and a control circuit coupled to the switching stage. The control circuit detects a threshold for changing between a synchronous operation mode and an asynchronous operation mode, synchronizes the detected threshold with a beginning of a new switching cycle, applies feed-forward compensation at the beginning of an ON-time period to vary a duty cycle, and generates drive signals to control the switching stage.

Abstract: Provided is a power supply control circuit for a power supply, including a PFC converter configured to generate a bus voltage, an electronic converter and an auxiliary power supply configured to generate an auxiliary supply voltage. The PFC converter comprises a PFC control circuit configured to drive the PFC converter to regulate the bus voltage to a requested value. When the output power is greater than the threshold, the power supply control circuit supplies the PFC control circuit with the auxiliary supply voltage. When the output power is smaller than the threshold, the circuit compares the bus voltage to upper and lower thresholds. When the bus voltage is greater than the upper threshold, the circuit inhibits supply of the PFC control circuit with the auxiliary supply voltage. When the bus voltage is smaller than a lower threshold, the circuit supplies the PFC control circuit with the auxiliary supply voltage.

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.

Abstract: The integrated circuit includes a power amplifier intended to provide a signal in a fundamental frequency band, an antenna, and a matching and filtering network having a first section, a second section, and a third section. The three sections include LC arrangements configured to have an impedance matched to the power amplifier's output in the fundamental frequency band. The LC arrangements of the first section and the second section are configured to have resonant frequencies adapted to attenuate the harmonic frequency bands of the fundamental frequency band.