Patents Assigned to STMICROELECTRONICS (GRENOVLE 2) SAS
  • Publication number: 20240010489
    Abstract: A MEMS device comprising: a semiconductor body defining a main cavity and forming an anchorage structure; and a first deformable structure having a first end and a second end that are opposite to one another along a first axis, the first deformable structure being fixed to the anchorage structure via the first end so as to be suspended over the main cavity. The second end is configured to oscillate, with respect to the anchorage structure, along a second axis. The first deformable structure comprises a main body having a first outer surface and a second outer surface, and a piezoelectric structure, which extends over the first outer surface. The main body comprises a bottom portion and a top portion that delimit along the second axis a first buried cavity aligned with the piezoelectric structure along the second axis, wherein a maximum thickness of the top portion of the main body along the second axis is smaller than a minimum thickness of the bottom portion of the main body along the second axis.
    Type: Application
    Filed: June 26, 2023
    Publication date: January 11, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Manuel RIANI, Gabriele GATTERE, Federico VERCESI
  • Patent number: 11869832
    Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Paolo Crema
  • Patent number: 11871668
    Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Paolo Ferrari, Flavio Francesco Villa, Luca Zanotti, Andrea Nomellini, Luca Seghizzi
  • Patent number: 11865581
    Abstract: An ultrasonic MEMS acoustic transducer formed in a body of semiconductor material having first and second surfaces opposite to one another. A first cavity extends in the body and delimits at the bottom a sensitive portion, which extends between the first cavity and the first surface of the body. The sensitive portion houses a second cavity and forms a membrane that extends between the second cavity and the first surface of the body. An elastic supporting structure extends between the sensitive portion and the body and is suspended over the first cavity.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Gabriele Gattere, Carlo Valzasina, Federico Vercesi, Giorgio Allegato
  • Patent number: 11869771
    Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuna′, Mario Giuseppe Saggio
  • Patent number: 11869944
    Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Simone Rascuná, Mario Giuseppe Saggio
  • Publication number: 20240003685
    Abstract: MEMS gyroscope, having a first movable mass configured to move with respect to a fixed structure along a first drive direction and along a first sense direction, transverse to the first drive direction; a first drive assembly, coupled to the first movable mass and configured to generate a first alternate drive movement; a first drive elastic structure, coupled to the first movable mass and to the first drive assembly, rigid in the first drive direction and compliant in the first sense direction; a second movable mass, configured to move with respect to the fixed structure in a second drive direction parallel to the first drive direction and in a second sense direction parallel to the first sense direction; a second drive assembly, coupled to the second movable mass and configured to generate a second alternate drive movement in the second drive direction; and a second drive elastic structure, coupled to the second movable mass and to the second drive assembly, rigid in the second drive direction and compliant
    Type: Application
    Filed: June 21, 2023
    Publication date: January 4, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Luca Giuseppe FALORNI, Patrick FEDELI, Gabriele GATTERE, Carlo VALZASINA, Paola CARULLI
  • Publication number: 20240006527
    Abstract: The present disclosure is directed to an electronic device including a semiconductor body having a first electrical conductivity and provided with a front side; an active area of the semiconductor body, accommodating the source and gate regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region of the electronic device, surrounding the active area. The edge region accommodates at least in part: i) an edge termination region, having a second electrical conductivity opposite to the first electrical conductivity, extending into the semiconductor body at the front side; and ii) a gate connection terminal of conductive material, electrically coupled to the gate region, extending on the front side partially superimposed on the edge termination region and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Salvatore CASCINO, Alfio GUARNERA, Mario Giuseppe SAGGIO
  • Patent number: 11860223
    Abstract: A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Giorgio Maiellaro, Angelo Scuderi, Angela Bruno, Salvatore Scaccianoce
  • Patent number: 11862757
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier Zanellato, Remi Brechignac, Jerome Lopez
  • Patent number: 11864361
    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Francesco Salamone
  • Patent number: 11862707
    Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Alfonso Patti, Alessandro Chini
  • Publication number: 20230420341
    Abstract: A power module includes a support, a first control contact area on the support, a second control contact area on the support, a first electronic power device, a second electronic power device, a first clip, a second clip, a third clip, and a package embedding the support, the first and the second electronic power devices as well as partially the first, the second and the third clips. The first electronic power device has a first conduction pad electrically coupled to the first clip, a second conduction pad electrically coupled to the third clip, and a control pad coupled to the first control contact area. The second electronic power device has a first conduction pad electrically coupled to the third clip, a second conduction pad electrically coupled to the second clip, and a control pad coupled to the second control contact area.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 28, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Sergio SAVINO
  • Publication number: 20230421039
    Abstract: Provided is a control device is for a switching voltage regulator having a switching circuit. The control device receives input and output voltages of the switching circuit and a measurement signal indicative of a current of the switching circuit. The control device has: a feedback module that detects an error signal indicative of a difference between the output voltage and a nominal voltage, and provides a control signal as a function of the error signal; a threshold-correction module that provides offset and ramp signals; and a driving-signal generation module coupled to the feedback and threshold-correction modules, which receives the measurement signal, compares the measurement signal with a threshold and, in response, provides a modulated signal for driving the switching circuit. The threshold is a function of the control, offset and ramp signals. The threshold-correction module provides the offset signal as a function of the input or output voltages.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 28, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Stefano CASTORINA, Elena BRIGO, Ivan FLORIANI
  • Publication number: 20230418559
    Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Michele ROSSI, Thomas BOESCH, Giuseppe DESOLI
  • Publication number: 20230420557
    Abstract: A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 28, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Angelo MAGRI', Stefania FORTUNA
  • Patent number: 11853765
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: December 26, 2023
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Michael Peeters, Fabrice Marinet
  • Patent number: 11855830
    Abstract: An input signal has a desired signal component and an interfering signal component superimposed thereon. Interfering component estimation processing is applied to the input signal, obtaining as a result a filtered signal comprising a sequence of filtered data samples. The filtered signal is subtracted from the input signal obtaining as a result an output signal comprising a sequence of output data samples. The interfering component estimation processing applies conjugating processing to the input signal, providing a conjugated version of the input signal. An adaptive signal processing coefficient is computed and adaptive signal processing is applied to the conjugated version of the input signal using the adaptive processing coefficient.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 26, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Alessandro Barbieri, Fabio Dell'Orto
  • Patent number: 11852676
    Abstract: An integrated circuit includes a sub-system and a reference sub-system. The reference sub-system is substantially identical to the sub-system but is non-operating by default. The integrated circuit includes a test circuit that obtains a parameter value of the sub-system and a reference parameter from the reference sub-system. The integrated circuit detects deterioration of the sub-system based on the parameter value and the reference parameter. The integrated circuit deactivates the sub-system and activates the reference sub-system responsive to detecting deterioration of the sub-system.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 26, 2023
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Carlo Caimi, Massimiliano Pesaturo, Stefano Antonio Mastrorosa, Alfredo Lorenzo Poli, Marco Della Seta
  • Patent number: 11854809
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: December 26, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuna', Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali