Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

Abstract: A depth map sensor includes a first array of first pixels, each first pixel having a first photodetector associated with a pixel circuit that comprises a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels. The first circuit is configured to receive the plurality of phase-shifted clock signals. The first circuit includes a first block and a second block. The first block is configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal and the second block configured to select to which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied.

Abstract: A process for manufacturing MEMS devices, includes forming a first assembly, which comprises: a dielectric region; a redistribution region; and a plurality of unit portions. Each unit portion of the first assembly includes: a die arranged in the dielectric region; and a plurality of first and second connection elements, which extend to opposite faces of the redistribution region and are connected together by paths that extend in the redistribution region, the first connection elements being coupled to the die. The process further includes: forming a second assembly which comprises a plurality of respective unit portions, each of which includes a semiconductor portion and third connection elements; mechanically coupling the first and second assemblies so as to connect the third connection elements to corresponding second connection elements; and then removing at least part of the semiconductor portion of each unit portion of the second assembly, thus forming corresponding membranes.

Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.

Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.

Abstract: A method of manufacturing a semiconductor package with an one or more dice present within a transparent resin, which may be an epoxy-based transparent resin or a silicone-based transparent resin, includes coupling the one or more dice to respective surfaces of a plurality of base portions of a panel substrate. Each one of the respective surfaces is between ones of a plurality of walls of the panel substrate that protrude from the respective surfaces of the panel substrate. A plurality of wirebonds may be formed to provide electrical pathways between the one or more dice and conductive structures of the panel substrate accessible at the respective surfaces of the panel substrate. A transparent resin may be formed to fill recesses or cavities between ones of the plurality of walls, and the panel substrate may then be singulated along the plurality of walls.

Abstract: A microelectromechanical membrane transducer includes: a supporting structure; a cavity formed in the supporting structure; a membrane coupled to the supporting structure so as to cover the cavity on one side; a cantilever damper, which is fixed to the supporting structure around the perimeter of the membrane and extends towards the inside of the membrane at a distance from the membrane; and a damper piezoelectric actuator set on the cantilever damper and configured so as to bend the cantilever damper towards the membrane in response to an electrical actuation signal.

Abstract: A control circuit for a switching stage of an electronic converter is described. The control circuit includes a driver circuit configured to generate one or more drive signals as a function of a Pulse-Width Modulation, PWM, signal and a PWM signal generator circuit configured to generate the PWM signal. A first comparator asserts a comparison signal when a feedback signal having a voltage being indicative of a current flowing through an inductance of the switching stage is greater than a reference signal. In response to a clock signal, a storage element asserts the PWM signal, whereby the clock signal indicates the duration of the switching period of the PWM signal. Conversely, in response to determining that the comparison signal is asserted, the storage element de-asserts the PWM signal. Specifically, the reference signal is generated as a function of the voltage at a capacitance.

Abstract: Various embodiments provide an ejection device for a fluid. The ejection device includes a first semiconductor wafer, housing, on a first side thereof, a piezoelectric actuator and an outlet channel for the fluid alongside the piezoelectric actuator; a second semiconductor wafer having, on a first side thereof, a recess and, on a second side thereof opposite to the first side, at least one inlet channel for said fluid fluidically coupled to the recess; and a dry-film coupled to a second side, opposite to the first side, of the first wafer. The first and the second wafers are coupled together so that the piezoelectric actuator and the outlet channel are set directly facing, and completely contained in, the recess that forms a reservoir for the fluid. The dry-film has an ejection nozzle.

Abstract: A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.

Abstract: In an embodiment, an USB interface includes a transformer, a primary winding of the transformer and a first switch connected in series between a first node and a second node, a secondary winding of the transformer and a component connected in series between a third node and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.

Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.

Abstract: In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.

Abstract: In an embodiments, a method for operating a time-of-flight (ToF) ranging array includes: illuminating a field-of-view (FoV) of the ToF ranging array with radiation pulses; receiving reflected radiation pulses with a plurality of single photon avalanche diodes (SPADs) in a region of interest (ROI) of the ToF ranging array, the plurality of SPADs arranged in a plurality of SPAD clusters; determining an ambient count of ambient light events generated by SPADs of a first SPAD cluster of the plurality of SPAD clusters; and gating an output of the first SPAD cluster based on the ambient count.

Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.