Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

Abstract: The present disclosure is directed to micro-electromechanical system (MEMS) accelerometers that are configured for a user interface mode and a true wireless stereo (TWS) mode of an audio device. The accelerometers are fabricated with specific electromechanical parameters, such as mass, stiffness, active capacitance, and bonding pressure. As a result of the specific electromechanical parameters, the accelerometers have a resonance frequency, quality factor, sensitivity, and Brownian noise density that are suitable for both the user interface mode and the TWS mode.

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

Abstract: A microelectromechanical resonator device has: a main body, with a first surface and a second surface, opposite to one another along a vertical axis, and made of a first layer and a second layer, arranged on the first layer; a cap, having a respective first surface and a respective second surface, opposite to one another along the vertical axis, and coupled to the main body by bonding elements; and a piezoelectric resonator structure formed by: a mobile element, constituted by a resonator portion of the first layer, suspended in cantilever fashion with respect to an internal cavity provided in the second layer and moreover, on the opposite side, with respect to a housing cavity provided in the cap; a region of piezoelectric material, arranged on the mobile element on the first surface of the main body; and a top electrode, arranged on the region of piezoelectric material, the mobile element constituting a bottom electrode of the piezoelectric resonator structure.

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Abstract: The present disclosure relates to a method implemented by a first NFC device, wherein the establishment of a transaction with a second NFC device configured in reader mode is performed when the signal level received by the first device, configured in card mode, reaches a first threshold, depending on the type of modulation technology of the second device.

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

Abstract: First combinational, arithmetic, or combinational and arithmetic, operations are applied to data and an expected value, generating result bit sequences. When the value of the data corresponds to the expected value, the result bit sequences are different from each other and correspond to expected values of the result bit sequences. Second operations are applied a first memory address, a second memory address, and the result bit sequences, generating a memory address. When values of the generated result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address. When values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address. A software routine starting at the generated memory address is executed.

Abstract: A circuit includes an electronic switch configured to be coupled intermediate a high-voltage node and low-voltage circuitry and configured to couple the low-voltage circuitry to the high-voltage node. A voltage-sensing node is configured to be coupled to the high-voltage node via a pull-up resistor. A further electronic switch can be switched to a conductive state to couple the voltage-sensing node and the control node of the electronic switch. A comparator compares a threshold with a voltage at the voltage-sensing node and causes the further electronic switch to switch on in response to the voltage at said voltage-sensing node reaching said threshold. A charge pump coupled to the current flow-path of the electronic switch is activated to the conductive state to pump electric charge from the current flow-path of the electronic switch to the control node of the electronic switch via the further electronic switch switched to the conductive state.

Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.

Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.

Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

Abstract: The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

Abstract: A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

Abstract: An indirect time-of-flight measurement sensor includes a photosensitive pixel array configured to acquire a succession of images of a scene during a given exposure time. The sensor includes a control unit configured to control the acquisition of the succession of images by the pixel array and to define an exposure time for this acquisition based on a pixel saturation rate of the array, distances between the sensor and elements of the scene, and a standard deviation of the distances between the sensor and the elements of the scene.

Abstract: A sensor includes detection circuitry and control circuitry coupled to the detection circuitry. The detection circuitry generates a detection signal indicative of a detected physical quantity. The control circuitry, in operation receives the detection signal and a frequency-indication signal, and generates a trigger signal based on the frequency-indication signal and a set of local reference signals. The sensor generates a digital output signal and a locking signal based on the trigger signal and the detection signal. The generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The locking signal is temporally aligned with the digital output signal.