Patents Assigned to STMICROELECTRONICS (GRENOVLE 2) SAS
  • Patent number: 12125762
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: October 22, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuna', Claudio Chibbaro, Alfio Guarnera, Mario Giuseppe Saggio, Francesco Lizio
  • Patent number: 12118451
    Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 15, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS INTERNATIONAL B.V.
    Inventors: Giuseppe Desoli, Thomas Boesch, Nitin Chawla, Surinder Pal Singh, Elio Guidetti, Fabio Giuseppe De Ambroggi, Tommaso Majo, Paolo Sergio Zambotti
  • Patent number: 12119024
    Abstract: A back electromotive force (BEMF) of a spindle motor in a hard disk drive is rectified and exploited to drive a voice coil motor (VCM) in the hard disk drive to retract the heads of the hard disk drive to a park position. The VCM is driven in a discontinuous mode comprising an alternation of VCM on-times and VCM off-times. Rectifying the BEMF of the spindle motor is discontinued before the end of the VCM off-times, Toff with the spindle motor brought into a brake condition wherein the spindle motor is short-circuited and the spindle BEMF forces currents through the windings of the spindle motor. The spindle current is thus pre-charged and made ready to cope with a VCM current request at the next VCM on-time.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: October 15, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Ezio Galbiati
  • Patent number: 12118146
    Abstract: An electronic device capable of determining an eye convergence angle using a magnetometer sensor is provided. The magnetometer sensor is capable of reporting angle readings in three dimensions that is aligned with an eye gaze direction of each eye of a user. The magnetometer which is incorporated into the device can fit into a human eye like a contact lens and determine the angle of the gaze direction of both eyes with respect to an object within a field of view. By obtaining this eye convergence angle for an object, it is possible to accurately detect depth information. The electronic device also functions as a digital contact lens that can automatically adjust the focal point of the object to provide the user with a clear vision. The electronic device also includes a display that provides the user with additional information about the object.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: October 15, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Dominique Paul Barbier
  • Publication number: 20240339464
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 10, 2024
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
  • Patent number: 12113103
    Abstract: A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 8, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Antonello Santangelo, Giuseppe Longo, Lucio Renna
  • Publication number: 20240329674
    Abstract: The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cesare BIMBI, Salvatore Giuseppe PRIVITERA, Francesco PULVIRENTI
  • Patent number: 12107144
    Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: October 1, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 12106201
    Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 1, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Carmine Cappetta, Thomas Boesch, Giuseppe Desoli
  • Patent number: 12105143
    Abstract: A digital-to-analog converter (DAC) includes a switching network and built-in-self-test (BIST) circuitry. The DAC, in operation, generates analog output signals in response to input codes of a set of input codes of the DAC. The BIST circuitry sequentially applies codes of a determined subset of codes of the set of input codes to test the plurality of switches. The determined subset of codes has fewer codes than the set of input codes. The BIST circuitry detects failures of switches of the plurality of switches based on responses of the DAC to the applied codes. In response to detecting a failure of a switch, the BIST generates a signal indicating a failure of the switching network.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: October 1, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Leonardo Pedone, Simone Scaduto, Rossella Gaudiano, Matteo Brivio, Matteo Venturelli
  • Publication number: 20240317450
    Abstract: Tray for containing electronic components formed by a bearing body, substantially planar, having a first and a second face. First holding structures extend from the first face of the bearing body and second holding structures extend from the second face of the bearing body. Each second holding structure is aligned with a respective first holding structure in a vertical direction perpendicular to the first and the second faces of the bearing body. Each first holding structure is formed by first protrusions mutually spaced by first spaces and arranged along a first closed line; each second holding structure is formed by second protrusions mutually spaced by second spaces and arranged along a second closed line. Each second protrusion is aligned, in parallel with the vertical direction, with the first spaces and each first protrusion is aligned, in parallel with the vertical direction, with the second spaces.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Massimiliano PESATURO, Massimo GREPPI
  • Patent number: 12101104
    Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: September 24, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Roberto Modaffari, Paolo Pesenti
  • Publication number: 20240307876
    Abstract: An analysis unit formed by an analysis body housing an analysis chamber and having a sample inlet and a supply channel configured to fluidically connect the sample inlet to the analysis chamber. Dried assay reagents are arranged in the analysis chamber and are contained in an alveolar mass. For instance, the alveolar mass is a lyophilized mass formed by excipients and by assay-specific reagents.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Marco CEREDA, Lillo RAIA, Danilo PIROLA
  • Patent number: 12094985
    Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: September 17, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Simone Rascuna′, Mario Giuseppe Saggio
  • Publication number: 20240304224
    Abstract: The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 12, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Christophe GONCALVES, Marc BATTISTA, Francois TAILLIET
  • Publication number: 20240304237
    Abstract: The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 12, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Christophe GONCALVES, Marc BATTISTA, Francois TAILLIET
  • Patent number: 12088085
    Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: September 10, 2024
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics International N.V.
    Inventors: Manoj Kumar, Ravinder Kumar, Nicolas Demange
  • Patent number: 12087368
    Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 10, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Arpit Vijayvergia, Vikas Rana
  • Patent number: 12087683
    Abstract: A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 10, 2024
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Guilhem Bouton
  • Patent number: 12085393
    Abstract: A user context and/or activity detection device envisages a pressure sensor, configured to provide a pressure signal; an electrostatic-charge-variation sensor, configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the user; and a processing unit, which is coupled to the pressure sensor and to the electrostatic-charge-variation sensor so as to receive the pressure signal and the charge-variation signal and is configured to jointly process the pressure signal and charge-variation signal for detecting changes in level or altitude.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: September 10, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Enrico Rosario Alessi, Fabio Passaniti