Abstract: The MEMS device has: a sensor body having a functional structure configured to transduce a physical or chemical quantity into a corresponding electrical quantity; and a cap bonded to the sensor body and having a first cavity overlying the functional structure. The cap has a supporting portion and a cover portion that form the first cavity. The supporting portion is bonded to the sensor body. The cover portion is bonded to the supporting portion and has an inner wall delimiting on a side the first cavity and facing the functional structure. The MEMS device further has a first coating that extends within the first cavity on the inner wall of the cover portion.

Abstract: A frequency modulation MEMS triaxial gyroscope, having two mobile masses; a first and a second driving body coupled to the mobile masses through elastic elements rigid in a first direction and compliant in a second direction transverse to the first direction; and a third and a fourth driving body coupled to the mobile masses through elastic elements rigid in the second direction and compliant in the first direction. A first and a second driving element are coupled to the first and second driving bodies for causing the mobile masses to translate in the first direction in phase opposition. A third and a fourth driving element are coupled to the third and fourth driving bodies for causing the mobile masses to translate in the second direction and in phase opposition. An out-of-plane driving element is coupled to the first and second mobile masses for causing a translation in a third direction, in phase opposition.

Abstract: Tray for containing electronic components formed by a bearing body, substantially planar, having a first and a second face. First holding structures extend from the first face of the bearing body and second holding structures extend from the second face of the bearing body. Each second holding structure is aligned with a respective first holding structure in a vertical direction perpendicular to the first and the second faces of the bearing body. Each first holding structure is formed by first protrusions mutually spaced by first spaces and arranged along a first closed line; each second holding structure is formed by second protrusions mutually spaced by second spaces and arranged along a second closed line. Each second protrusion is aligned, in parallel with the vertical direction, with the first spaces and each first protrusion is aligned, in parallel with the vertical direction, with the second spaces.

Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.

Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

Abstract: An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.

Abstract: In an embodiment, a method includes: receiving data signals from a plurality of pixels of an array of pixels; generating a plurality of signal-to-noise ratios by determining signal-to-noise ratios for each respective pixel of the plurality of pixels on the basis of the data signals received from the respective pixel; and filtering the data signals received from each pixel of the plurality of pixels by using an adaptive filter configured on the basis of the plurality of the signal-to-noise ratios to generate filtered data signals.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

Abstract: A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.

Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task.

Abstract: Provided are techniques for protecting a transaction in near-field communication. Provided is an electronic device including a processor hosting an application, a near-field communication module, and a secure element distinct from the processor. The near-field communication module is configured to identify the type of terminal emitting a polling frame, addressed to the application, that the communication module receives by analyzing the type of the polling frame. The device is configured to compare the result of the analysis with at least one command received from the terminal during the implementation of an NFC transaction.

Abstract: The present disclosure relates to a near-field communication device including a near-field communication controller. The near-field communication controller includes at least one first demodulator, adapted to apply a first type of demodulation to a first signal modulated according to a first or a second type of modulation; and at least one second demodulator, adapted to apply a second type of demodulation to the first signal.

Abstract: A microfluidic device for continuous ejection of fluids includes: a semiconductor body that laterally delimits chambers; an intermediate structure which forms membranes each delimiting a top of a corresponding chamber; and a nozzle body which overlies the intermediate structure. The device includes, for each chamber: a corresponding piezoelectric actuator; a supply channel which traverses the intermediate structure and communicates with the chamber; and a nozzle which traverses the nozzle body and communicates with the supply channel. Each actuator is configured to operate i) in a resting condition such that the pressure of a fluid within the corresponding chamber causes the fluid to pass through the supply channel and become ejected from the nozzle as a continuous stream, and ii) in an active condition, where it causes a deformation of the corresponding membrane and a consequent variation of the pressure of the fluid, causing a temporary interruption of the continuous stream.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: An electronic device includes a processor and one or more secure elements. The processor executes a first high-level operating system and a first application. The one or more secure elements execute a first low-level operating system to verify a reliability, an authenticity, or a reliability and an authenticity of the first high-level operating system, and execute a second low-level operating system to execute a second application and to perform wireless communication with the first application. At each booting of the electronic device, the first low-level operating system performs a verification of the reliability, of the authenticity, or of the reliability and the authenticity of the first high-level operating system. In response to a request from the first application to the second application, the second low-level operating system requests a result of the verification from the first low-level operating system, and transmits the result to the second application.

Abstract: An electronic device includes a secure element and an application programming interface. The secure element, in operation, executes a first application. The application programming interface, in operation, verifies a reliability of a received command directed to the first application, and transmits the command and a result of the verification to the first application.

Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

Abstract: An analysis unit formed by an analysis body housing an analysis chamber and having a sample inlet and a supply channel configured to fluidically connect the sample inlet to the analysis chamber. Dried assay reagents are arranged in the analysis chamber and are contained in an alveolar mass. For instance, the alveolar mass is a lyophilized mass formed by excipients and by assay-specific reagents.