Abstract: A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.

Abstract: A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is claimed. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed.

Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: An amplifier in which a clamping circuit is an integral part of the output stage structure is used as a voice coil driver for positioning the heads of a memory disk drive. The output stage, operating in class AB, comprises two bipolar transistors, the source and the sink transistors, serially connected between a power supply and a ground terminal, the serial connection between the emitter of the first transistor and the collector of the second transistor being the output terminal of the output stage. The base terminals of the two output transistors are connected to a bias circuit and to an input transistor, used as the signal control element. The clamping circuit is directly connected with the base terminals of the output transistors to limit the voltage on said base terminals between a first and a second voltage reference.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: The contact opening through an insulating layer is formed having a straight sidewall portion and a bowl shaped sidewall portion. The bowl shaped sidewall portion is near the top of the insulation layer to provide an enlarged diameter of the contact opening at the top relative to the bottom. A conductive material is then formed in the contact opening in electrical contact with a lower conductive layer. The conductive material forms a plug having an enlarged head, such as a nail head or a flat heat screw shape. The enlarged head protects the silicon and a barrier layer, if present, within the contact from being etched by any subsequent anisotropic etches. Thus, when an electrical interconnection layer such as aluminum is formed overlying the contact plug, the plug acts as an etch stop to prevent etching of a barrier layer of the barrier layer within the contact opening.

Abstract: A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at the surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate electrode is formed over a substrate having source/drain regions adjacent to the gate electrode and in the substrate. A silicon dioxide layer is formed over the gate electrode and a portion of the substrate not covered by the gate electrode. A first phosphorous doped spin-on-glass layer is formed over the silicon dioxide layer, wherein the spin-on-glass is doped to a concentration sufficient to facilitate gettering of charge mobile ions. An opening is then formed in the spin-on-glass layer and the silicon dioxide layer exposing a portion of the source drain region.

Abstract: A structure formed during processing of an integrated circuit. Two layers of photoresist are formed over a conductive layer to be patterned. The lower layer is thinner than the upper layer, and is dyed to have a lower transmittance. Both layers are used as a masking pattern for the underlying conductive layer.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: Methods and apparatuses are provided for use in driving a multiple-phase brushless motor. The methods and apparatuses include generating a slewed phase control signal for each phase of the motor. The slewed phase control signals are substantially proportional to a speed control signal during non-transitioning periods, and are slewed from one state to the next state over time during transitioning periods. The transitioning periods being associated with a commutation point. The slewed phase control signals are used to generate pulse width modulated (PWM) driving signals, for each phase of the motor. Thus, the shape of the resulting PWM driving signal will include additional PWM pulses during the transitioning period that provide for a trapezoidal shaping of the current supplied to each of the phase coils in the motor. The result is that torque ripple is reduced because the overall current applied to the motor and the torque resulting therefrom will tend to be more constant during commutation.

Abstract: A power-switched driver circuit for a disc drive that provides accurate back emf detection in PWM mode. In one embodiment, a power transistor is coupled between the low side drivers and ground. During the off time of a PWM cycle, all of the high side drivers are off and the current recirculates through two of the low side drivers. The power transistor is off. This disconnects the motor from ground and allows the voltage on the center tap of the motor to be about half of V.sub.cc, which allows the back emf of the motor to be detected during the off time using a conventional comparator as the back emf approaches a zero crossing. During the on time of a PWM cycle, the power transistor is on.In an alternative embodiment, a power transistor is coupled between the high side drivers and V.sub.cc. During the off time of a PWM cycle, all of the low side drivers are turned off and the current recirculates through two of the high side drivers. The power transistor is off, disconnecting the motor from V.sub.

Abstract: A liquid level sensor unit outputs a voltage value which corresponding to a measured liquid level to an improved anti-slosh circuit that provides a fast timing rate during the initial condition of the circuit and a slow timing rate during the normal operation of the circuit. The improved anti-slosh circuit further includes a low liquid level warning circuit and a power-on-reset circuit. The system timing rate can be externally controlled by connecting an RC circuit to the improved anti-slosh circuit. Customer defined reference level for low liquid warning is also possible. The entire circuit is included on a single, monolithic integrated circuit. An input pin receives the signal from the fuel tank. An output pin drives a liquid level gauge.

Abstract: A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simulation circuit includes a memory cell replicate which replicates the time required for writing data to memory cells of the array. After the memory cell replicate has changed state, a signal is output via a switching circuit to the variable timer circuit for generation of a write termination signal. The memory cells are tested at various write cycle speeds by controlling the variable timer circuit. The variable timer circuit is set to terminate the write as quickly as possible after a successful write to the memory cells has been completed.

Abstract: A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

Abstract: A circuit for operating a polyphase DC motor, such as the type having a plurality of "Y" connected stator coils, has circuitry for charging the coils at a rate which will reduce EMI and other noise, while maintaining an acceptable charge rate. The gate of a selected high side driving transistor is charged at a relatively high rate during a ramping phase. During the ramping phase, the gates of the selected transistor is charged to a voltage near the voltage needed to form a channel in the transistor for conduction. After the ramping phase, the gates are charged at a lesser rate in order to control the rate of charging of the stator coils to prevent noise.

Abstract: A method of forming vias in an interlevel dielectric structure of an integrated circuit, such that the aspect ratio of the vias is smaller than the aspect ratios of vias having a height equal to the thickness of the entire interlevel dielectric structure, and the integrated circuit formed according to such a method. Conductive elements are formed over an insulator. A first dielectric structure is formed over the conductive elements and over the insulator. The first dielectric structure contains a first dielectric, formed over the conductive elements and the insulator, and a planarizing dielectric, formed over the first dielectric to bulk fill the areas between the conductors. A thin layer of a second dielectric can be formed over the first dielectric and the planarization dielectric. Vias are patterned and etched in the first dielectric structure. The thickness of the first dielectric structure is such that the aspect ratios of the vias through it is close to, or less than, 1.

Abstract: A field-effect transistor structure is described having a monocrystalline silicon channel region which is epitaxially continuous with an underlying monocrystalline silicon body region. Polycrystalline silicon source and drain regions abut the channel region. The source and drain regions are electrically isolated from the underlying body region by a patterned dielectric layer, which may include a thick field oxide. A polycrystalline silicon gate is capacitively coupled with the channel region by a second dielectric layer. The gate may extend laterally to partly overlap the source and drain regions.

Abstract: A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.

Abstract: An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In one embodiment, the lamp voltage is compared to a reference waveform, such as a sinusoid. The switches are activated responsive to the error between the lamp voltage and reference waveform to minimize the error. The lamp can thus be driven with a closer approximation of the reference waveform.