Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

Abstract: A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load capable of operating at either of several consumption levels when the load changes its power consumption level. The load transient compensator has a comparator having an output connected to an input of an upper driver and of a lower driver with the output of each of the driver being connected to a gate of a power transistor. When the load is in sleep mode and is about to start being accessed, the upper driver is turned on to turn on its associated transistor to supply additional current to the load, regulated by the comparison circuit. When the load is in the power up mode and it is about to stop being accessed, the lower driver is turned on to turn on its associated transistor to drain current supplied to the load by a supply, regulated by the comparison circuit.

Abstract: Disclosed is an electrical technique for clamping the bitline voltage above zero volts in a DRAM circuit. The technique may be used in embedded DRAM arrays implemented in logic-based technology employing low threshold voltages. The invention employs a low voltage generator to provide a bitline voltage slightly above zero volts. Applying this slightly elevated level to the input of a DRAM cell access transistor effectively increases the threshold voltage of that transistor and thus limits sub-threshold leakage current. The low voltage generator may be implemented as a cascode circuit with supplemental current sources.

Abstract: Disclosed is a method and associated apparatus for compensating for kTC noise in individual pixels of an MOS imaging array. The kTC noise at issue forms when a pixel is disconnected from a reset voltage by turning off an MOS transistor which controls access to the pixel photodiode. Compensation is accomplished by first exposing the photodiode to the reset voltage and then disconnecting the well region from V.sub.dd to cause it to float. By allowing the well to float, the kTC charge subsequently introduced (at the conclusion of the reset process) redistributes so that most of it accumulates on the capacitor between the well and the substrate. Later, the well is reclamped to V.sub.dd, and the noise contribution stored in the well-substrate capacitor is canceled. A disclosed apparatus includes an array of pixels, each having a separate well. In addition, access of the well to a source of power (V.sub.dd) must be switchable. Therefore, a transistor is included at each pixel's connection to a V.sub.dd.

Abstract: A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.

Abstract: According to the present invention, entry into the test mode of an integrated circuit device is possible even when there is no device pin dedicated to a test mode function. Test mode control circuitry allows a pin of the integrated circuit device to be double mapped to a normal operation function and to a test mode function. The test mode control circuitry has a polarity circuit having a polarity bond pad and a fuse circuit having a fuse element, either of which may determine when the polarity of the pin is representative of a test mode function. Either down-bonding the polarity bond pad to the lead frame of the integrated circuit device or blowing the fuse renders the pin representative of the test mode function. Additionally, once the test mode of the device is entered, the device may be adequately stress tested.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.

Abstract: An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In one embodiment, the lamp voltage is compared to a reference waveform, such as a sinusoid. The switches are activated responsive to the error between the lamp voltage and reference waveform to minimize the error. The lamp can thus be driven with a closer approximation of the reference waveform.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Abstract: A circuit device for selecting operating modes using a single reference pin that uses current rather than voltage in an electronic subsystem. An operating mode is selected by modulating the input bias current over a range of values. A specific range is associated with a given function so that a value of current can assume a parametric input into the subsystem. The circuit has widespread application since current can be modulated faster than voltage and it eliminates the need for multiple voltage reference points.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance C.sub.gd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors in each phase combination. The sense FETs are operably connected to one side of the current mirror circuit. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. At the same time, the time to reach the threshold is measured and the phase combination having the longest time is stored.

Abstract: Disclosed is a multiport SRAM cell. The cell state may be switched by controlling the potential on a single bit line only. A true dual port SRAM cell (in which the two ports may be accessed nearly simultaneously without needing peripheral arbitration logic) employs two cross-coupled inverters, two bit lines, two word lines, and two access transistors. The SRAM cells employ internal "pseudo inverters" that can be independently powered on and off. By powering one of them off during the write operation, the internal conflict associated with changing the value of a stored bit is avoided. Each pseudo inverter may be powered on and off via a pseudo ground or a pseudo Vdd line which controls the potential to locations where ground or Vdd are normally supplied to CMOS inverters.

Abstract: A fingertip-operated solid state capacitance switch detects a capacity change that is induced by the physical contact of an ungrounded fingertip to an external dielectric surface of the solid state switch. The input and output of a solid state signal-inverting amplifier are respectively connected to two relatively large and ungrounded capacitor plates that are associated with, but electrically isolated from, the switch's external dielectric surface. An ungrounded fingertip forms a third capacitor plate on the switch's external surface. The solid state amplifier detects the presence of a fingertip on the switch's external surface by way of a change in capacitance within a compound, three plate, capacitor that includes the two ungrounded capacitor plates and the ungrounded fingertip that is resident on the switch's external surface.

Abstract: A method is provided for forming isolated regions of oxide of an integrate circuit, and an integrated circuit formed according to the same. A plurality of active areas is formed in an upper surface of a portion of a substrate body. A field oxide region is formed which separates at least two of the plurality of the active areas, wherein an upper surface of the field oxide region is substantially planar with an upper surface of the substrate body. Nitride spots are formed in the bulk of the field oxide region and not in the active area which do not need to be removed since they do not effect device integrity.

Abstract: A tri-state I/O buffer and a method of inhibiting current to an I/O buffer arranged to be powered by a supply voltage and to drive an output terminal are provided. The I/O buffer preferably has an output driving circuit connected to the supply voltage for driving the output terminal and includes a first plurality of transistors defining an isolated floating well circuit for operatively connecting the output terminal to the supply voltage and a second plurality of transistors defining a pull-down circuit for operatively connecting the output terminal to ground. An input control circuit is connected to the output driving circuit and the supply voltage, and is arranged to receive a buffer input signal for controlling the buffer input signal to the output driving circuit.

Abstract: A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I.sub.bias). The bias current (I.sub.bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4.sub.beta and mirrored again by a factor "c" on the output of DMOS2. The same I.sub.bias is mirrored by a ratio "b" and multiplied by the product of Q5.sub.beta and Q6.sub.beta. The push-pull current operation at the output terminal (416) is obtained by turning on and off switches SW1 (418) and SW2 (420) that are controlled by a clock signal. The voltage regulator (400) further includes an output voltage clamp (424) that keeps control of the V.sub.boost voltage by controlling the amount of bias current (I.sub.bias).