Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: An integrated circuit wherein a planarization step has been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.

Abstract: A circuit for producing multiple pulse width modulated outputs. The circuit includes a logic device for each pulse width modulated output. Each of the logic devices includes a first input, a second input, and a clock input, and each of logic device produces a logical high output in response to a logical high at its first input in coincidence with a clock signal at its clock input. The logical high output of the logic device remains high until a logical high is applied at its second input in coincidence with a clock signal at the clock input, whereupon the logic device produces a logical low output. The logical low output of the logic device remains low until a logical high is again applied at its first input in coincidence with a clock signal at the clock input. The circuit includes programmable circuitry for selectively applying logical high and low signals to the first and second inputs of the logic devices.

Abstract: An integrated circuit device such as an SRAM operating in a battery backup mode, or operating in a quiescent mode when deselected in the operation of a portable electronic device, includes a power dissipation control circuit that reduces the voltage on an internal power supply node so that the memory array is powered at a minimum level sufficient to retain the data stored therein intact.

Abstract: A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the level of the input signal. The enable signal may be the sense-amplifier enable signal. The signal driver may also include an input circuit that receives the input signal and generates an intermediate signal from the input signal when the enable signal has the first state. An output circuit is coupled to the input circuit, receives the intermediate signal, and generates the output signal from the intermediate signal. A switch circuit is coupled to the input circuit, receives the enable signal, and cuts off substantially all supply current to the input circuit when the enable signal has the second state.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: Parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by multiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

Abstract: A high performance CMOS process using grown field oxide for active area isolation takes advantage of process steps used in LDD transistor fabrication to reduce the chip space occupied by the field oxide. Portions of the spacer oxide layer are retained intact over the field oxide during the etching step used to form the oxide spacers on the sides of the polysilicon gates. The retained spacer oxide portions increase the total oxide thickness in the field area to effectively block the ion implantation used to form the heavily doped portions of the source and drain regions. This enables use, in the initial fabrication steps, of a grown field oxide of reduced thickness and advantageously a correspondingly reduced width so as to reduce the chip space allocated to the field oxide.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract: A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the interconnect pads of the integrated circuit, coupled to the processor during normal operation mode of the circuit, to the memory during a memory test mode; (2) and decoupling the external interconnect pads from the memory, after the memory is tested, and coupling them to the processor.

Abstract: A liquid level sensor unit outputs a voltage value, which corresponds to a measured liquid level, to an anti-slosh circuit that provides a fast timing rate during the initial condition of the circuit and a slow timing rate during the normal operation of the circuit. The anti-slosh circuit further includes a low liquid level warning circuit and a power-on-reset circuit. The system timing rate can be externally controlled by connecting an RC circuit to the improved anti-slosh circuit. A customer defined reference level for low liquid warning is also possible. The entire circuit is included on a single, monolithic integrated circuit. An input pin receives the signal from the fuel tank. An output pin drives a liquid level gauge.

Abstract: A method is provided for reducing the reflectivity of a metal layer prior to photolithography. A thin buffer layer, such as oxide, can be deposited over the metal layer. A short plasma etch is performed in order to roughen, but not completely remove, the thin oxide layer. This roughened layer significantly reduces the reflectivity of the underlying metal layer. As an alternative, the brief plasma etch can be applied directly to the metal layer, which results in a significant roughening of its upper surface. This also reduces the reflectivity of the metal layer.

Abstract: A DVD CD-ROM player integrated with a personal computer is provided. When integrating a DVD CD-ROM with a personal computer, there are various problems that must be overcome. For example, the stream from the DVD CD-ROM utilizes a 27 MHz clock. However, a personal computer typically does not have a 27 MHz clock, but instead has a system clock, that runs at the frequency of the processor. Therefore, in order to play a DVD-based audio-visual work in a personal computer, a clock running at 27 MHz is needed. As such, a software clock running at 27 MHz is provided which facilitates the integration of a DVD CD-ROM into a personal computer. By using a software clock, synchronization of the audio-visual stream is facilitated and both cost and development time are reduced.

Abstract: An integrated circuit and method are provided for generating current for low power applications. The integrated circuit preferably includes a current generating circuit responsive to a supply voltage for generating a first reference current and a temperature compensating voltage controlling circuit for generating a temperature compensated voltage control signal during temperature variations. A bias controlling circuit is preferably connected to the current generating circuit and the temperature compensating voltage control circuit for biasingly controlling the temperature compensating voltage control circuit. A current output controlling circuit is connected to the current generating circuit and the temperature compensating voltage controlling circuit for controlling a second temperature compensated reference current responsive to the temperature compensated voltage control signal so as to generate a high output source current even during low temperature conditions.

Abstract: An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.

Abstract: An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a channel of the first conductivity type, and a second MOSFET is connected to the first MOSFET and has a channel of a second conductivity type. The second MOSFET is preferably biased to a pinch-off region and cooperates with the first MOSFET for generating a control signal related to an effective threshold voltage of the first MOSFET. Moreover, the circuit preferably generates a bias voltage to the plurality of MOSFETs and to the first MOSFET based upon the control signal to set an effective threshold voltage of the plurality of MOSFETs to have an absolute value less than an absolute value of the initial threshold voltage and, more preferably, to a reference voltage. Accordingly, lower supply voltages can be readily accommodated.

Abstract: A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

Abstract: A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the level of the input signal. The enable signal may be the sense-amplifier enable signal. The signal driver may also include an input circuit that receives the input signal and generates an intermediate signal from the input signal when the enable signal has the first state. An output circuit is coupled to the input circuit, receives the intermediate signal, and generates the output signal from the intermediate signal. A switch circuit is coupled to the input circuit, receives the enable signal, and cuts off substantially all supply current to the input circuit when the enable signal has the second state.

Abstract: A circuit and method to clamp a node of a power device connected to a driving node of a polyphase d-c motor to a reference potential during a powering off of the drive includes a current mirror and a comparator. A first input of the comparator is connected to the reference potential, and a second input is connected to the driving node. The reference potential may be a ground potential, or, preferably, the potential at another driving node of the motor. An output of the comparator is connected to a first side of the current mirror. A circuit is connected to apply a current reflecting the output of the comparator to a low side driver connected to the node.