Abstract: In a high current, high frequency integrated circuit chip characteristic of producing an excess of internal on-chip circuit induced noise with respect to a low current, low frequency circuit implemented on the high current, high frequency integrated circuit chip, a method is disclosed for reducing noise in the low current, low frequency circuit. The method includes placing noise sensitive components of the low current, low frequency circuit external to the integrated circuit chip, corresponding to an off-chip placement. An exclusive power supply reference line V.sub.(REF) tapped off of a power supply bus internal to the integrated circuit chip is provided. The exclusive power supply reference line V.sub.(REF) is tapped off the internal power supply bus on-chip at a physical location proximate the low current, low frequency circuit and routed off-chip. The noise sensitive components are connected between the low current, low frequency circuit and the power supply reference line V.sub.

Abstract: An apparatus and method for underfilling a silicon chip (16) to a substrate (12) by depositing an underfill dam (18) on the surface (20) of the substrate (12) prior to addition of the underfill material (14), is disclosed. A bead of underfill material (14) is provided on the substrate (12) about the periphery of the silicon chip (16), within the underfill dam (18). The underfill material (14) fills the gap (22) between the electrical contacts, the substrate (12) and the silicon chip (16) by capillary action and differential pressure created by a vacuum system (40).

Abstract: A low noise preamplifier design which is configured such that the current through the first stage load resistor may be made relatively small in value making it possible to achieve a relatively large gain in the first stage thereby reducing the noise contribution of the load resistor and, concurrently, significantly reducing the noise contribution of the second stage as well. This is effectuated by supplying a substantially fixed amount of current to certain nodes in the first stage of the preamplifier through a pair of current sources, the currents being of an amount sufficient to subtract out the bias current that is applied through a series connected variable resistance, such as that of a magnetoresistive ("MR") read head. As a consequence, only a relatively small amount of current is actually fed through the load resistor, and its value may be increased to provide an increased gain for the first stage.

Abstract: The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.

Abstract: An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute value of an effective threshold voltage of each MOSFET to be lower than an absolute value of the initial threshold voltage. Accordingly, the effective threshold voltages may set to below a predetermined value, and lower supply voltages thereby readily accommodated. For integrated circuits having all n-channel MOSFETs, the threshold voltages are positive, and the voltage divider can be set accordingly. The invention is advantageously also used in CMOS integrated circuits having both p-channel and n-channel MOSFETs. The resistor voltage divider may preferably be set or trimmed after forming the MOSFETs.

Abstract: A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array.

Abstract: A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive element, an amplifier, and the power device. Both the first and second switches receive a control signal. The elements of the driver circuit are configured such that the conductive device will conduct only when the following two conditions are met: the control signal is a certain logic level and the voltage generated by the amplifier is larger than a reference voltage. When the control signal transitions from a first to a second logic state, a charging current is delivered to the capacitive element, an output voltage of the driver circuit increased to the reference voltage, and a voltage on a control terminal of the power device also increases to a charge pump voltage level.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. The plurality of MOSFETs preferably includes at least one MOSFET having a first conductivity type and at least one MOSFET having a second conductivity type. Each MOSFET has an initial threshold voltage. The integrated circuit also preferably includes first and second biasing circuits which selectively bias only a selected well a corresponding conductivity type of the plurality of MOSFETs to produce an absolute value of an effective threshold voltage of only the selected MOSFET which is lower than an absolute value of the initial threshold voltage thereof and thereby inhibit a high standby current for the integrated circuit. Method aspects of the invention are also disclosed.

Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.

Abstract: The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal expansion coefficient than the metal plug. The hole is heated such that the metal in the hole flows to eliminate the void as a result of the compressive stress generated by the cap layer on the metal plug.

Abstract: A set of circuits for controlling the slew rate of a driving transistor in a rotating three-phase DC motor having a "Y" configuration of coils. The slew rate is reduced when the rotational speed of the motor is low. The slew rate is controlled by controlling the voltage applied to a control terminal of the driving transistor. The voltage applied to the control terminal of the driving transistor is selected in response to a control signal that is indicative of the speed of the motor.

Abstract: A circuit for controlling the slew rate at a motor coil during turn-on in a commutation sequence is disclosed. The disclosed circuit includes a switched current mirror that receives the commutation signal, and that provides a mirrored current to the input of an integrating buffer amplifier when its associated coil is to be driven. The integrating buffer amplifier includes an amplifier with a feedback capacitor, and a current source connected at its input, for reducing the voltage slew rate during turn-off of the transistor. The mirrored current applied to the input on the integrating buffer amplifier is greater than that of the current source, but limited so as to reduce the voltage slew at the coil.

Abstract: A voltage regulator for producing an output voltage that selectively tracks a logic voltage or a reference voltage and method of operating the voltage regulator. The voltage regulator has a diode OR with a logic and reference transistors. The logic voltage is scaled to be close in value to the reference voltage, if the two are not close in value. When the scaled logic voltage is larger than the reference voltage the logic transistor is on, turning off the reference transistor and passing the logic voltage to the output of the diode OR. When the scaled logic voltage is smaller than the reference voltage the logic transistor is off and the reference transistor is on, passing the reference voltage to the output of the diode OR. The voltage at the output of the diode OR is then compared in a comparator with the voltage at the output of the voltage regulator, which is scaled by the same factor as the logic voltage.

Abstract: An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, a sacrificial layer on the fixed contact layer, and a floating contact on the sacrificial layer and having portions thereof overlying the fixed contact layer in spaced relation therefrom in an open switch position and extending lengthwise generally transverse to a predetermined direction. The floating contact preferably includes at least two layers of material. Each of the at least two layers have a different thermal expansion coefficient so that the floating contact displaces in the predetermined direction responsive to a predetermined temperature variation so as to contact the fixed contact layer and thereby form a closed switch position.

Abstract: A special rail is provided along each edge of an integrated circuit chip with bias circuits connected to the ends of each special rail. The bias circuits charge the special rail to the V.sub.DD voltage level during normal operation, and clamp the special rail to the V.sub.SS rail upon the occurrence of an overvoltage event. Input bonding pads are provided along each edge of the chip and are connected through diodes to the special rail so that 5 volt signals applied to the input bonding pads do not cause damage to the device when operated from a 3.3 volt supply. A signal line of extended length is provided between each input bonding pad and its receiver circuit and includes folded portions for adding to the length of the signal line to form a high frequency inductor to protect the receiver circuit at the onset of an overvoltage event before clamping becomes effective.

Abstract: According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock control logic circuitry of the present invention is characterized as having at least a first delay timing chain, a second delay timing chain, and means for selectively changing the width of a self-timed pulse generated by the clock control logic circuitry. Selectively changing the width of the self-timed pulse is accomplished by selectively adding the delay of the first delay timing chain to the delay of the second delay timing chain during a special mode of operation of the clocked memory device.

Abstract: A DC-to-DC converter includes an error amplifier; a ramp generator for generating a ramp signal at the first input of the error amplifier independent of the output of the error amplifier and so that the output of the error amplifier ramps up at a relatively slow rate to avoid overshoot of the desired output voltage of the converter during the start-up phase of the converter; and a ramp disable circuit for disabling the ramp signal upon reaching a value corresponding to the normal operating phase of the converter. The DC-to-DC converter preferably includes at least one power switch and pulse width modulation (PWM) control circuit cooperating with the power switch to provide a desired output voltage of the converter. The ramp generator in one embodiment comprises a current source and an external capacitor connected thereto. In yet another embodiment, the ramp generator may be provided by a staircase ramp generator comprising an amplifier and an integrating capacitor connected thereto.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.