Abstract: A method for making a semiconductor device may include forming, above a substrate, a stack of alternating layers of first and second semiconductor materials. The second semiconductor material may be different than the first semiconductor material. The method may further include forming fins from the stack, with each fin having alternating layers of the first and second semiconductor materials, and selectively removing sidewall portions of the second semiconductor material from the fins to define recesses therein. The method may also include forming a dielectric material within the recesses, forming additional first semiconductor material on sidewall portions of the first semiconductor material in the fins, and forming a dielectric layer overlying the fins to define nanowires including the first semiconductor material within the dielectric layer.

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract: A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions. At least the side walls of the fin structures in the second region are covered with an epitaxially grown layer of second semiconductor material. A drive in process is performed to convert the fin structures in the second region from the first semiconductor material to the second semiconductor material. The first semiconductor material is, for example, silicon, and the second semiconductor material is, for example, silicon germanium or silicon carbide. The fin structures in the first region are provided for a FinFET of a first (for example, n-channel) conductivity type while the fin structures in the second region are provided for a FinFET of a second (for example, p-channel) conductivity type.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: After completely etching through a material stack comprising an oxide hard mask layer and an underlying interlevel dielectric (ILD) layer formed on a substrate to provide at least one opening, top corners of the at least one opening are rounded by performing a plasma etch employing a combination of an etching gas and a deposition gas comprising a hydrofluorocarbon compound. The hydrofluorocarbon compound forms a hydrofluorocarbon polymer layer on sidewalls of the at least one opening and helps to preserve the profile of the at least one opening.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Abstract: A photonic integrated circuit includes optical circuitry fabricated over an underlying circuitry layer. The optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract: Embodiments of the present disclosure are directed to MOCA networks including power-saving MOCA-capable devices. Each of the MOCA-capable devices is operable during a normal or active mode to perform the specific multimedia functionality for which the device is designed, such as to function as a digital video recorder (DVR) and content server, set-top box, and so on. Moreover, each of the MOCA-capable devices is also operable to automatically enter a low-power or standby mode, which reduces the power consumption of the device, when the device need not operate in the active mode. In this way, power savings in each of the MOCA devices results in overall power savings in the MOCA network. A global user-configurable low-power or standby mode parameter can be utilized to override the automatic standby mode operation if desired.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: In an embodiment, a transmitter includes first and second transmission paths. The first transmission path is configurable to generate first pilot clusters each including a respective first pilot subsymbol in a first cluster position, and the second transmission path is configurable to generate second pilot clusters each including a respective second pilot subsymbol in a second cluster position such that a vector formed by the first pilot subsymbols is orthogonal to a vector formed by the second pilot subsymbols. For example, where such a transmitter transmits simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) over respective channels that may impart inter-carrier interference (ICI) to the signals due to Doppler spread, the pattern of the pilot symbols that compose the pilot clusters may allow a receiver of these signals to use a recursive algorithm, such as a Vector State Scalar Observation (VSSO) Kalman algorithm, to estimate the responses of these channels.

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.