Abstract: In one embodiment of this invention, identical communicating node elements are constructed and placed throughout a power delivery network. Each of these node elements supplies features and options that facilitate peer-to-peer communications, data and service aggregation, propagated interfaces and distributed computational power. The network of interacting node elements, built with a common architecture, gives the power delivery network advanced capabilities for utilities and customers. These advanced capabilities include self-healing, highly secure communications, real-time interactions between any devices, and so on.

Abstract: A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an “acknowledgement” that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.

Abstract: A wireless sensor network including a plurality of Smart Sensors coupled to a wide area network such as the Internet via a Wireless Sensor Coordinator. Each wireless sensor network comprises a plurality of Smart Sensors, each operable to measure one or more physical quantities. Each wireless sensor communicates the measured data to a Wireless Sensor Coordinator which then stores the collected data in memory. The Wireless Sensor Coordinator further includes a web server operable to post a web site on a network that is accessible by a common web browser. Upon receiving a request for sensed data via the web site, the Wireless Sensor Coordinator retrieves the appropriate measured and stored data and converts it into HTML format pages which are then posted on the web site for review by the requestor.

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract: This invention relates to switching power saving modes and rescheduling communication frames for various periods of a beacon interval (BI) defined under WGA Draft Specification 0.8 for the personal basic service set (PBSS) and infrastructure BSS to achieve further power savings and other advantages. Stations can be awake during a contention-based period (CBP) if it is in active state and can schedule frames during a service period (SP) to allow the assigned receiver to transmit to the assigned initiator. Stations in a group can schedule a group address frame to be sent during the CBP and group SP of a specific periodic BI. Stations in peer-to-peer connection may directly notify its peer stations of its power saving mode and wakeup schedule. Stations of an infrastructure basic service set (BSS) can also use the same power saving mechanism as stations of a PBSS noting a difference where each BI will be an access point's (AP's) awake BI.

Abstract: An additional cyclic redundancy check (CRC) is inserted in IEEE 802.11 beacon or data frames prior to the end of the frame, at a location following information sufficient for the receiving station to determine whether the frame is from an overlapping basic service set or intended for a different station and to extract other necessary or useful information such as a time of the next full beacon. Upon detecting the CRC, the receiving STA can terminate reception of the frame early to conserve power, and then enter a low power operational mode to further conserve power.

Abstract: Multiple virtual MAC addresses may be added to WGA devices that may have different traffic streams to another device that requires different services, thus creating distinct MAC and device level implications. Beamforming training can be done at the device level for all virtual MAC addresses. Wakeup, doze, and ATIM power save can be done at the device level depending on the frames received. Authentication, deauthentication, association, and deassociation can be done variously at both levels. Further MSDUs can be aggregated for the multiple MAC addresses.

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract: A device for correlating trend data with respect to a patient's weight and lower extremity displacement can identify conditions indicative of congestive heart failure. An imaging mechanism is operable to measure lower extremity displacement over a period of time. An over-time trend analysis of both the patient's weight and the lower extremity displacement measurements is performed to determine whether over a particular sample period an increase in a patient's lower extremity displacement can be correlated with an increase in the patient's weight. When such a correlation does not exist, an alert can be issued of conditions indicative of congestive heart failure.

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract: Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.