Abstract: A method of manufacturing a modular semiconductor subassembly: providing at least one semiconductor subassembly having a modular sidewall element of modular dimensions and a semiconductor substrate base element coupled to the modular sidewall element that has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element. If a modular package protective cover is to be used: providing the modular package protective cover configured to accommodate the semiconductor subassembly in accordance with a modular design; securing the semiconductor subassembly in the modular package protective cover to create a modular package assembly; and mounting the modular package assembly to a core, with a base side of the semiconductor substrate base element in contact with the core; otherwise: mounting the at semiconductor subassembly to the core, with the base side of the semiconductor substrate base element in contact with the core.

Abstract: A validation system includes a test block that operates to apply a set of inputs to a system under test, such as a test system or an executable test algorithm, and receive from said system under test a first set of outputs produced by operation of the system under test in response to application of the set of inputs. The first set of outputs, as well as a second set of outputs reflecting output produced by operation of a reference system or executable reference algorithm in response to application of the same set of inputs, is processed to make a validation determination. A validation processing block compares the first and second sets of outputs to validate the system under test as an equivalent to the reference system.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract: A system includes a primary functionality and a backup functionality for the primary functionality. A measurement circuit measures operational parameter values of the primary functionality. A fault detection circuit determines a level of equivalence between the operation of the primary functionality and a reference functionality based on a weighted comparison of the measured operational parameter values of the primary functionality to corresponding reference operational parameter values for the reference functionality If the equivalence determination fails to find equivalence, the fault detection circuit signals a fault in the primary functionality and activates the backup functionality.

Abstract: A receiver is enabled to perform self-configuration of the main data link to receive and display video data. A video data signal is received through a data link having multiple channels or lanes at a specific bit rate. No link configuration data normally associated with the video signal is received. It is then determined which one or more of the channels of the data link are active in transmitting the data signal. A symbol pattern in the data signal is then identified. The symbol rate of the data signal is then synchronized with the local clock frequency. The local clock frequency is set to correspond to the actual bit rate of the data signal, thereby creating a signal-based clock frequency. This local clock frequency is set using only the data signal since no link configuration data associated with the signal is received. In this manner, the receiver configures or trains the link itself using only the video data signal and therefore, the receiver may be described as self-sufficient.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. Also at the same end is a serial interface connector, such as a serial interface connector. At the other end is an upgraded serial interface connector (e.g., enhanced serial interface) connector having high-speed transmission pins, high-speed receiving pins, and a ground pin, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously.

Abstract: In one embodiment of the present invention, motion compensated interpolation is performed by locating full frame conceal and reveal areas, determining intermediate frame occlusion areas of an interpolated frame of the displayable output by locating intermediate frame conceal areas based on projected locations of pixels within the full frame conceal areas using forward motion vectors and information about a time slot for the interpolated frame, and by locating intermediate frame reveal areas based on projected locations of pixels within the full frame reveal areas using backward motion vectors and information about the time slot for the interpolated frame; for any pixels in the interpolated frame to which there is neither a forward vector nor a backward vector projecting: including the pixel in an intermediate frame conceal area if it is not located within the full frame reveal area; including the pixel in an intermediate frame reveal area if it is not located within the full frame conceal area; and using the

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.

Abstract: In a typical powerline communications environment, all electrical outlets and branches are connected to a load center. In this type of electrical system, all communication devices will share the same frequency spectrum, limiting the maximum bandwidth of the network, where all nodes are in contention with each other. In the inventive system, the electrical load center would provide filtering to isolate all branches off the load center into different network segments all capable of carrying the maximum bandwidth allowed by the physical layer technology. The advantages of the method described by this invention will be most noticeable when high bandwidth devices are communicating with each other on the same electrical segment, for example a HDTV receiver communicating with a HDTV monitor in the same room.

Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Abstract: An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract: The invention presents a novel method to channel estimation in OFDM systems. The embodiment of this invention is a block of new logic and modifications performed to other components of the system, added to any existing OFDM receiver, which utilizes information available from other blocks as found in the receiver. This logic would improve the units' error rate because of the improved channel quality estimations it makes available. This improvement is made possible because both channel noise data and channel signal data are used in the estimation process. This data goes through a learning process over time and multiple data blocks for further improvements in the quality of the estimate. This improvement is possible without any direct communications with other remote units, but it could be used in a multi-node environment to improve the performance of the system as the whole.

Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack. The chip stack also includes an array of flexible conductors disposed between two chips, thereby providing an electrical connection between the two chips.

Abstract: A hierarchical WRAN includes a relay station (RS) possessing dual roles. A RS acts from the perspective of a base station (BS) as a consumer premise equipment (CPE) terminal just as any other first tier CPE terminal. Simultaneously, the RS, from the perspective of other second tier CPEs, acts as a BS providing all of the functional capabilities of a BS. The RS includes dual medium access control (MAC) functions in which a first MAC function serves to interface the RS with the BS while the second MAC function serves to interface the RS with the at least one CPE terminal. The RS further includes a convergence layer that maps, at the RS, the first MAC to the second MAC. The dual MAC capability of the RS enables the RS to pipeline frame transmission in both single and multi-channel operations.

Abstract: A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of processors. The concurrency engine is capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. The concurrency primitives could represent objects, and the processors may be capable of using the objects by reading from and/or writing to addresses in an address space associated with the concurrency engine. Each address may encode an object index identifying one of the objects, an object type identifying a type associated with the identified object, and an operation type identifying a requested operation involving the identified object.

Abstract: According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal ions. The metal couples a conductor to another material. The metal and the conductor are exposed to an electrical field in such a manner that one or both of the metal and the conductor becomes an anode to a corresponding cathode. The metal ions are then allowed to migrate from the anode to the cathode to form a migrated metal. Finally, a migration inhibitor is applied on top of the migrated metal to prevent further migration.

Abstract: A method for uniformly planarizing a wafer that includes determining a first wafer warped value at a first zone on the wafer, determining a second wafer warped value at a second zone on the wafer, and calculating a pressure difference based on the first and second wafer warped values at the first and second zones is provided. The method also includes performing a chemical mechanical polishing of the wafer, applying a first pressure based on the first wafer warped value to the wafer at the first zone during the chemical mechanical polishing, and applying a second pressure based on the second wafer warped value to the wafer at the second zone during the chemical mechanical polishing, a difference between the first pressure and the second pressure based on the pressure difference.