Abstract: Enhanced low power medium access (LPMA) processes involve the enhanced LPMA STA indicating low power capabilities during association and being allocated an AID. The AID(s) for one or a group of enhanced LPMA STA(s) are included in one TIM sent during a different BEACON interval than the AID(s) for another or another group of enhanced LPMA STA(s). In addition, or alternatively, the AID(s) for enhanced LPMA STA(s) are located at an edge of the AID set within a TIM, a portion of the TIM that may be easily truncated and therefore not sent. The enhanced LPMA STAs and associated access point negotiate unique offset and sleepinterval periods for polling or data uplink by the enhanced LPMA STAs.

Abstract: In order to satisfy the conflicting requirements for spectrum sensing and QoS of data transmission, it is highly desirable for a cognitive radio system, e.g. IEEE 802.22 WRAN, to perform spectrum sensing and data transmission simultaneously. Embodiments of the invention address critical issues of self-interference generated from a transmission unit to the co-located sensing unit when the simultaneous sensing and data transmission technique is applied. A number of interference mitigation techniques are described and analysis are given.

Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.

Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.

Abstract: An additional cyclic redundancy check (CRC) is inserted in IEEE 802.11 beacon or data frames prior to the end of the frame, at a location following information sufficient for the receiving station to determine whether the frame is from an overlapping basic service set or intended for a different station and to extract other necessary or useful information such as a time of the next full beacon. Upon detecting the CRC, the receiving STA can terminate reception of the frame early to conserve power, and then enter a low power operational mode to further conserve power.

Abstract: An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process.

Abstract: An apparatus for performing metrology of a wafer. The apparatus may include a substrate with a plurality of microprobes. A plurality of light sources may direct light onto each of the microprobes. Light reflected from the microprobes may be detected by a plurality of photodetectors thereby generating a detection signal associated with each of the microprobes. A controller may send a driving signal to each of the plurality of microprobes and determine a height profile and a surface charge profile of the wafer based on each of the detection signals.

Abstract: A semiconductor processing device and a method of operating the same. The method may include measuring at least one property of a semiconductor wafer and determining a recipe for processing the semiconductor wafer based on the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules based on the determined recipe, wherein the recipe comprises a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an inline metrology device. The recipe and various parameters associated with the recipe may be determined by a controller of the semiconductor processing device.

Abstract: Motion estimation systems and methods are disclosed. An apparatus may include a processing unit to acquire video images and to arrange the video images into a plurality of sequential video frames, and a motion estimation unit that receives the sequential video frames and determines a set of repetitive pattern neighbor candidate vectors for repetitive pattern content in a first frame. The set of repetitive pattern neighbor candidate vectors may be reduced by sorting the set to eliminate spurious repetitive pattern neighbor candidate vectors. The reduced set may be provided to a second adjacent frame. A method may include acquiring a plurality of sequential video frames having a repetitive pattern content, and determining a set of repetitive pattern neighbor candidate vectors for the repetitive pattern content in a first frame of the sequential video frames. The set of repetitive pattern neighbor candidate vectors may be sorted by determining at least one spurious repetitive pattern neighbor candidate vector.

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Abstract: Methods and systems are described for enabling improved interface between a dual-mode multimedia source that supports a pair of data formats and a sink device operable using inputs in a third data format. An adaptor device enabling improved connectivity as well as backward compatibility with legacy devices is disclosed. The system enables the transmission of sideband channel configured in an I2C over AUX format thereby enabling increased performance in sideband channels of a dual-mode source.

Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.

Abstract: Clustered VLIW processing elements, each preferably simple and identical, are coupled by a runtime reconfigurable inter-cluster interconnect to form a coprocessor executing only those portions of a program having high instruction level parallelism. The initial portion of each program segment executed by the coprocessor reconfigures the interconnect, if necessary, or is skipped. Clusters may be directly connected to a subset of neighboring clusters, or indirectly connected to any other cluster, a hierarchy exposed to the programming model and enabling a larger number of clusters to be employed. The coprocessor is idled during remaining portions of the program to reduce power dissipation.