Abstract: An apparatus and method are disclosed for a measurement system that reports as a measurement result a confidence interval associated with a histogram bin into which a measurement value falls. The confidence interval is calculated from a subset of training values that also fall within the histogram bin. A training process may be performed in which a plurality of training values is obtained and a mean and standard deviation of the values determined. A plurality of histogram bins are defined from the mean and standard deviation and, for the subsets of training values that fall into each bin, confidence intervals calculated. A need to perform the training process may be determined from a plurality of measured values.

Abstract: A wireless sensor network including a plurality of Smart Sensors coupled to a wide area network such as the Internet via a Wireless Sensor Coordinator. Each wireless sensor network comprises a plurality of Smart Sensors, each operable to measure one or more physical quantities. Each wireless sensor communicates the measured data to a Wireless Sensor Coordinator which then stores the collected data in memory. The Wireless Sensor Coordinator further includes a web server operable to post a web site on a network that is accessible by a common web browser. Upon receiving a request for sensed data via the web site, the Wireless Sensor Coordinator retrieves the appropriate measured and stored data and converts it into HTML format pages which are then posted on the web site for review by the requestor.

Abstract: Methods and systems are described for transmitting and displaying video data after a hot plug event during a start-up dead period. In particular, hot plug events occurring when a toggleable hot plug detection mechanism is used.

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract: A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.

Abstract: The present disclosure is directed to a system and method for forming a plurality of packaged dice on a carrier, the carrier including a storage medium configured to store an indication of a total number of unpackaged dice on the carrier. The forming includes providing a quantity of molding compound to a molding module based on the total number of the unpackaged dice on the carrier. The providing includes accessing the indication of the total number of the unpackaged dice on the carrier from the storage medium, determining the quantity of molding compound based on the indication of the total number of unpackaged dice on the carrier, and molding the unpackaged dice into the packaged dice using the quantity of molding compound.

Abstract: A multimedia sink device comprises: 1) a connector configured to be connected to an adaptor cable; 2) detection circuitry configured to detect when the adaptor cable is connected to the connector; and 3) hot plug detection (HPD) circuitry configured to determine if a configuration circuit is coupled to an HPD line of the multimedia sink device. In response to a determination that the configuration circuit is coupled to the HPD line, the HPD circuitry determines if the configuration circuit is associated with the adaptor cable. The HPD circuitry reads configuration data from the configuration circuit associated with the adaptor cable. The configuration data indicates the configuration circuit is resident in the cable adaptor and causes the multimedia sink device to increase a voltage level of a power supply voltage provided by the multimedia sink device to a multimedia source device via the adaptor cable.

Abstract: An interconnect arrangement includes a plurality of tag allocators. Each tag allocator is configured to receive at least one stream of a plurality of packet units and further configured to tag each packet unit. Each packet unit is tagged with one of a set of n tags where n is greater than two. At least one stream is tagged with a sequence of tags that is different from a sequence of tags used for at least one other of said streams. The interconnect arrangement also includes a router configured to receive a plurality of streams of tagged packet units and to arbitrate between the streams such that packet units having a same tag are output in a group.

Abstract: A boost circuit is used for power factor correction (PFC). In a low power application, transition mode control is utilized. However, switching frequency varies with different input voltages, and over a wide input voltage range, the switching frequency can become too high to be practical. To address this issue, a boost circuit is provided whose effective inductance changes as a function of input voltage. By changing the inductance, control is exercised over switching frequency.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: There is disclosed an apparatus for implementing special mode playback operations in a digital video recorder. The apparatus comprises an Intra frame indexing device capable of receiving an incoming MPEG video stream and identifying therein data packets associated with Intra frames, wherein the Intra frame indexing device modifies header information in a first data packet associated with a first Intra frame to include location information identifying a storage address of a second data packet associated with a second Intra frame.

Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack.

Abstract: A bandgap voltage reference circuit includes a current generation stage configured to generate a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current and to generate a reference current by combining the PTAT and CTAT currents. An output stage is coupled to the current generation stage and configured to combine the PTAT current and the CTAT current to generate a bandgap voltage reference. A curvature correction circuit is configured to generate a curvature correction current that mirrors the reference current generated from the PTAT and CTAT currents. The curvature correction current has a ratio relative to the reference current given by a current ratio parameter having value that is less than one, equal to one, or greater than one. In this way the value of the current ratio parameter can be varied to cancel a non-linear dependence on temperature of the bandgap voltage reference, thereby providing a curvature-compensated bandgap voltage reference.

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A wireless local area network system establishes a PASSPOINT™ connection between a mobile station and a hotspot using an enhanced single SSID method or an enhanced dual SSID method. In the dual SSID method, an access point associates and authenticates a mobile device to a secondary SSID of the access point during enrollment and provisioning. After enrollment, the access point authenticates the mobile station to a primary SSID of the access point using the credential that the mobile station received from an online sign-up (“OSU”) server in connection with the secondary SSID. In the single SSID method, an access point performs two levels of authentication. During authentication, communications are limited to an 802.1x controlled port running on the mobile station and access point. After a first authentication, communications between the OSU server and the mobile station are unblocked. After the second authentication, all traffic from the mobile station is unblocked.

Abstract: A IEEE 802.11 Wireless Local Area Network (WLAN) system of an access point (AP) and one or more stations (STAB) reduces power consumption and increases battery life of power efficient low power STAB by decreasing the amount of time that a power efficient low power STA remains in an awake state. After indicating power efficient low power operation during association with an AP supporting such operation, the power efficient low power STA may enter the doze state from the time that the power efficient low power STA sends a PS-Poll until the power efficient low power STA receives the buffered DATA frame from the AP. While implementing the power efficient PS-Poll method, the AP can send the buffered DATA frame to the STA SIFS after the AP sends an ACK to the received PS-Poll from the STA.