Abstract: A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data. The data processor generates the enhanced virtual image by generating a first component virtual image at a first depth plane, generating a second component virtual image at a second depth plane, and inserting first selected pixels from the first component virtual image into enhanced the virtual image and inserting second selected pixels from the second component virtual image into the enhanced virtual image.

Abstract: A method includes receiving first encoded data associated with one or more first lanes and decoding the first encoded data to produce decoded data. The method also includes encoding the decoded data to produce second encoded data associated with one or more second lanes and transmitting the second encoded data. In some embodiments, the method may further include multiplexing a plurality of code group sequences (the second encoded data) into the one or more second lanes, and the number of first lanes may be greater than the number of second lanes. In other embodiments, the method may also include demultiplexing a plurality of code group sequences from the one or more first lanes into a plurality of the second lanes, and the number of first lanes may be less than the number of second lanes.

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and in particular to a method of addressing zero-delay frequency switching for cognitive dynamic frequency hopping. The method combines regular (periodic) channel maintenance with dynamic frequency hopping over a cluster of vacated channels that are initially setup such that the switching delays for channel setup and channel availability check are eliminated.

Abstract: To allow a single LDPC decoder to operate on both 512 B blocks and 4 KB blocks with comparable error correction performance, 512 KB blocks are interlaced to form a 1 KB data sequence, and four sequential 1 KB data sequences are concatenated to form a 4 KB sector. A de-interlacer between the detector and decoder forms multiple data sequence from a single data sequence output by the detector. The multiple data sequences are separately processed by a de-interleaver between the de-interlacer and the LDPC decoder, by the LDPC decoder, and by an interleaver at the output of the LDPD decoder. An interlacer recombines the multiple data sequences into a single output. Diversity may be improved by feeding interleaver seeds for respective codewords into the de-interleaver and interleaver during processing.

Abstract: A common control channel for base station (“BS”)/consumer premise equipment (“CPE”) communication in areas of overlapping coverage by wireless regional area network (“WRAN”) cells operating on different working channels is disclosed. A common control channel is selected from among the various working channels sensed in each of a plurality of overlapping WRAN cells so as to enable BS/CPE and BS/BS communication. Once chosen, each CPE within the overlapping area communicates with the controlling BS via an enhanced coexistence beacon protocol messages. These messages include timing and other synchronization information.

Abstract: A plurality of resistive paths are coupled in parallel to a common node. A high side driver is operable responsive to first control signals to selectively supply current to certain ones of the resistive paths. A low side driver, including a plurality of selectively actuated current sink paths, is provided to sink current from the common node. A control logic circuit actuates a current sink path within the low side driver for each resistive path that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of resistive paths that are supplied current by the high side driver. A switched high side and low side configuration operating in an analogous way is also disclosed.

Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.

Abstract: A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady battery voltage value to the maximum and the minimum battery voltage values. If the measured steady state battery voltage value is greater than the maximum battery voltage value, an over voltage state is reported by the processor. If the measured steady state battery voltage value is less than the minimum battery voltage value, a low battery voltage state is reported by the processor.

Abstract: An integrated circuit for a smart card in accordance with an exemplary embodiment includes at least one data terminal for providing communications with a host device over a system bus and a processor configured to provide an attachment signal on the at least one data terminal for recognition by the host device. Further, the processor also cooperates with the host device to perform an enumeration based upon at least one default descriptor, and receive information from the host device regarding a system event. In addition, the processor is configured to remove the attachment signal from the at least one data terminal and thereafter again provide the attachment signal on the at least one data terminal based upon the information regarding the system event, and cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor.

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set.

Abstract: Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer.

Abstract: A system, apparatus and method are disclosed for separating a current frame of a composite video signal into a luminance signal and a chroma signal. A relative chroma correlation value is generated using a plurality of lines of the current frame. A weighted sum of inter-line pixel differences of the current frame is generated using the relative chroma correlation value. A frame difference signal is generated by subtracting a previous frame of the composite video signal from the current frame. A detected motion signal is generated that corresponds to motion detected in the current frame. The weighted sum of inter-line pixel differences, the frame difference signal, and the detected motion signal are combined to generate the chroma signal. The chroma signal is subtracted from the current frame to generate the luminance signal.

Abstract: Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.

Abstract: An integrated circuit for a smart card includes a plurality of data buffers and a processor. In particular, the processor selectively allocates data buffers from the plurality thereof and exchanges data therewith based upon different types of data. As such, the processor advantageously changes the allocation of the buffers for different data types based upon various bandwidth constraints in a particular smart card environment to enhance bandwidth utilization.

Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

Abstract: A parallel deblocking filtering method, and deblocking filter processor performing such deblocking, for removing edge artifacts created during video compression. The method includes loading luma samples for a macroblock. Filtering is performed on a set of vertical edges of the macroblock using information in the luma samples, with vertical edge filtering occurring concurrently with the loading of the luma samples. The method also includes filtering a set of horizontal edges of the macroblock using information in the luma samples. The horizontal edge filtering occurs in parallel with vertical edge sampling and with loading operations. The use of parallel and concurrent operations significantly enhances the efficiency of the deblocking method. Storing of filtered samples is also performed in the method, and this storing is performed concurrently with some loading operations as well as filtering operations. Edge filtering includes performing filtering to the H.264 standard and its deblocking filtering algorithm.

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract: A plurality of resistive paths are coupled in parallel to a common node. A high side driver is operable responsive to first control signals to selectively supply current to certain ones of the resistive paths. A low side driver, including a plurality of selectively actuated current sink paths, is provided to sink current from the common node. A control logic circuit actuates a current sink path within the low side driver for each resistive path that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of resistive paths that are supplied current by the high side driver. A switched high side and low side configuration operating in an analogous way is also disclosed.

Abstract: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.

Abstract: The present disclosure is directed to method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.