Patents Assigned to STMicroelectronics, Inc.
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Publication number: 20120154273Abstract: A method and apparatus for touch detection, multi-touch detection and cursor control in which the acceleration of a control surface is sensed to provide sensed signals. The control surface is supported at one or more support positions and moves in response to a force applied by a user at a touch position. The sensed signals are received in a processing unit where they are used to estimate a change in the position of force application. A touch control signal is generated from the estimated change in touch position. The touch control signal may be output to a graphical user interface, where it may be used, for example, to control various elements such as mouse clicks, scroll controls, control of single or multiple cursors, or manipulation of views of an object on a visual display unit, or remote control manipulation of objects themselves.Type: ApplicationFiled: March 1, 2011Publication date: June 21, 2012Applicant: STMicroelectronics, Inc.Inventors: Darryn D. McDade, SR., Hamid Mohammadi
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Publication number: 20120155652Abstract: When two loudspeakers play the same signal, a “phantom center” image is produced between the speakers. However, this image differs from one produced by a real center speaker. In particular, acoustical crosstalk produces a comb-filtering effect, with cancellations that may be in the frequency range needed for the intelligibility of speech. Methods for using phase decorrelation to fill in these gaps and produce a flatter magnitude response are described, reducing coloration and potentially enhancing dialogue clarity. These methods also improve headphone compatibility and reduce the tendency of the phantom image to move toward the nearest speaker.Type: ApplicationFiled: February 21, 2012Publication date: June 21, 2012Applicant: STMICROELECTRONICS, INC.Inventor: Earl C. VICKERS
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Publication number: 20120156847Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: STMicroelectronics Inc.Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
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Publication number: 20120157151Abstract: Three alternative methods of controlling transmit power in a basic service set (BSS) including a plurality of stations that have successfully synchronized with an access point include providing each BSS with one transmit power limit that is not more than the lowest one of the transmit power limits of all of its operating channels, providing each BSS with one transmit power limit that is fixed for physical layer convergence procedure (PLCP) protocol data units (PPDU) with each channel bandwidth, or providing each BSS with one transmit power limit that is fixed for each 80 MHz channel.Type: ApplicationFiled: December 16, 2010Publication date: June 21, 2012Applicant: STMicroelectronics, Inc.Inventors: Liwen Chu, George A. Vlantis
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Publication number: 20120155797Abstract: Disclosed is a photonic integrated circuit having a plurality of lenses and a method for making the same. The photonic integrated circuit is comprised of optical circuitry fabricated over an underlying circuitry layer. In some embodiments, the optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.Type: ApplicationFiled: April 13, 2011Publication date: June 21, 2012Applicant: STMicroelectronics, Inc.Inventor: John Hongguang Zhang
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Publication number: 20120155195Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Applicant: STMicroelectronics Inc.Inventor: David V. Carlson
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Patent number: 8202668Abstract: A fuel cell device includes a housing containing a fuel processor that generates fuel gas and a fuel cell having electrodes forming an anode and cathode, and an ion exchange electrolyte positioned between the electrodes. The housing can be formed as first and second cylindrically configured outer shell sections that form a battery cell that is configured similar to a commercially available battery cell. A thermal-capillary pump can be operative with the electrodes and an ion exchange electrolyte, and operatively connected to the fuel processor. The electrodes are configured such that heat generated between the electrodes forces water to any cooler edges of the electrodes and is pumped by capillary action back to the fuel processor to supply water for producing hydrogen gas. The electrodes can be formed on a silicon substrate that includes a flow divider with at least one fuel gas input channel that can be controlled by a MEMS valve.Type: GrantFiled: March 31, 2009Date of Patent: June 19, 2012Assignee: STMicroelectronics, Inc.Inventor: Anthony M. Chiu
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Patent number: 8203506Abstract: An LED array includes a plurality of LED segments connected in a common cathode configuration at a common cathode node. A high side driver is operable responsive to segment control signals to selectively supply current to certain LED segments. A low side driver is provided to sink current from the common cathode node. A plurality of selectively actuated current sink paths are provided in each low side driver. A control logic circuit actuates a current sink path within the low side driver for each LED segment that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of LED segments that are supplied current by the high side driver so as to achieve a substantially constant LED segment brightness. A common anode configuration operating in an analogous way is also disclosed.Type: GrantFiled: April 6, 2005Date of Patent: June 19, 2012Assignee: STMicroelectronics, Inc.Inventor: Eric Danstrom
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Publication number: 20120146152Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: STMICROELECTRONICS, INC.Inventor: Barry Dove
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Patent number: 8198865Abstract: A method and integrated circuit for preserving a battery's charge and protecting electrical devices is disclosed. A maximum and a minimum battery voltage value at the output port are stored in a memory. A steady state battery voltage at the output port is measured and stored in the memory. A processor compares the measured steady battery voltage value to the maximum and the minimum battery voltage values. If the measured steady state battery voltage value is greater than the maximum battery voltage value, an over voltage state is reported by the processor. If the measured steady state battery voltage value is less than the minimum battery voltage value, a low battery voltage state is reported by the processor.Type: GrantFiled: August 4, 2010Date of Patent: June 12, 2012Assignee: STMicroelectronics, Inc.Inventors: Marian Mirowski, Gary J. Burlak
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Patent number: 8199707Abstract: A self-coexistence window reservation protocol for a plurality of Wireless Regional Area Network (WRAN) cells operating in a WRAN over a plurality of channels includes a sequence of self-coexistence windows that uniquely identifies a transmission period for each WRAN cell. A self-coexistence window reservation protocol is included within the first packet of a Coexistence Beaconing Protocol period identifying when each WRAN cell associated with a particular channel will transmit. When not actively transmitting, a WRAN cells remains in a passive, receiving mode to accept data. As the transmissions of each WRAN cell operating on a particular channel are scheduled, contention for a transmission period is eliminated.Type: GrantFiled: May 9, 2008Date of Patent: June 12, 2012Assignee: STMicroelectronics, Inc.Inventor: Wendong Hu
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Publication number: 20120139114Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.Type: ApplicationFiled: December 6, 2010Publication date: June 7, 2012Applicant: STMicroelectronics, Inc.Inventors: John Hongguang Zhang, Cindy Goldberg, Walter Kleemeier, Ronald Kevin Sampson
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Publication number: 20120142121Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.Type: ApplicationFiled: December 6, 2010Publication date: June 7, 2012Applicant: STMICROELECTRONICS, INC.Inventors: Prasanna Khare, Nicolas Loubet, Qing Liu
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Patent number: 8193595Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.Type: GrantFiled: December 31, 2009Date of Patent: June 5, 2012Assignees: STMicroelectronics, Inc., STMicroelectronics Asia Pacific Pte Ltd.Inventors: Venkatesh Mohanakrishnaswamy, Olivier Le Neel, Loi N. Nguyen
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Publication number: 20120135776Abstract: A method and apparatus for conserving power in a wireless communication device. The method includes receiving at least a portion of a PHY protocol data unit (PPDU) frame, where the PPDU frame includes an aggregate MAC protocol data unit (A-MPDU) field. The method also includes comparing a receiver address (RA) within the A-MPDU field to a stored address of the wireless communication device and, if the received RA does not match the stored address, causing power to be removed from one or more circuits of the wireless communication device for a calculated period of time.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: STMicroelectronics, Inc.Inventors: Liwen Chu, George A. Vlantis
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Publication number: 20120134324Abstract: A method and apparatus for negotiating an idle subchannel set for a wireless data transmission. The method includes transmitting an indication of a first set of idle subchannels to a wireless station. The method also includes receiving an indication of a second set of idle subchannels from the wireless station. The method further includes determining a final set of idle subchannels based on the indication of the first set of idle subchannels and the indication of the second set of idle subchannels.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: STMicroelectronics, Inc.Inventors: Liwen Chu, George A. Vlantis
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Patent number: 8187975Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.Type: GrantFiled: December 6, 2010Date of Patent: May 29, 2012Assignee: STMicroelectronics, Inc.Inventors: Prasanna Khare, Nicolas Loubet, Qing Liu
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Patent number: 8183806Abstract: A back EMF signal from PWM driven motor is passed through an attenuation circuit. The attenuation circuit has a first mode of operation and a second mode of operation. The first mode of operation, used to sample a higher voltage back EMF signal during PWM on-time, applies the back EMF signal to a resistive divider formed of a first resistor and second resistor connected in series. The second mode of operation, used to sample a lower voltage back EMF signal during PWM off-time, applies the back EMF signal to a circuit comprised of a transistor conduction path in series with the second resistor. A control signal, responsive PWM on-time and off-time state, controls switching between the first and second modes.Type: GrantFiled: June 8, 2009Date of Patent: May 22, 2012Assignee: STMicroelectronics, Inc.Inventor: Dennis C. Nolan
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Publication number: 20120120205Abstract: An accelerated black frame is inserted into an output vertical blanking period, keeping the output VBI at the same length or shorter than the input VBI. The output VBI is not extended. Input video data is received at a frame memory at a first transmission rate during an input active frame period. The video data is transmitted from the frame memory to a display at a second transmission rate during an output active frame period. The second transmission rate is faster than the first rate, which would normally lead to an extended output VBI. The transmitting (pouring in of data into the frame buffer) ends at the same time as all the data has been received at the monitor (drained). A black data frame which consists of meaningless data is inserted into the output VBI such that the output VBI is not longer than the input VBI.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: STMICROELECTRONICS, INC.Inventor: Osamu KOBAYASHI
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Publication number: 20120122373Abstract: A method and system for detecting and controller wafer surface pressure distribution. Detecting and controlling wafer surface pressure distribution comprises measuring in situ wafer uniformity of a wafer at a plurality of locations of the wafer; and in response to the measured wafer uniformity controlling through a feedback loop in situ CMP head pressure applied at the plurality of locations of the wafer in real time to polish the wafer.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: STMICROELECTRONICS, INC.Inventors: John H. Zhang, Paul Ferreira, Cindy Goldberg