Abstract: An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors. To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used. Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value. One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors.

Abstract: An image sensor includes an array of pixels arranged in rows and columns. A reference current source provides the reference current to a transistor forming one half of a current mirror. Each column has a current source, which forms the other half of a current mirror. A switch is provided to selectively connect a resistance between ground and the transistor. When the resistance is connected, the transistor is starved of gate-source voltage, which reduces the current supplied by each current source.

Abstract: A geometric processing stage for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage includes: a model view module for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives, a back face culling module arranged downstream of the model view module for at least partially eliminating the non visible primitives, a projection transform module for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and a perspective divide module for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). The back face culling module is arranged downstream the projection transform module and operates on normalized projection (P) coordinates of said primitives.

Abstract: A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

Abstract: A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Abstract: A polarization sensitive solid state image sensor includes an integrated photodetector and polarizing assembly. The polarizing assembly is formed directly on an upper dielectric surface of the photodetector as a metal grid. The integral form of the device improves polarization operation and reduces manufacturing costs.

Abstract: A packet switch for switching cells comprising fixed-size data packets.

Abstract: The method of processing a first digital image by combining the first digital image with a second digital image includes the first digital image being received from a pixel array, and when receiving the first digital image it is converted into a first continuous sequential data stream. The second digital image may be provided in the form of a second continuous sequential data stream, and the first and second digital images may be combined by continuously combining the data in the first and second data stream.

Abstract: A method is for generating a key from the fixed pattern noise (FPN) of a CMOS image sensor to be used in generating a digital authentication signature. The key may be generated by temporarily disabling the FPN cancellation circuit that is conventionally included in the system, and generating a substantially “black” image to produce a digitized FPN signal. The key may then be generated from characteristics of the FPN, such as by comparing pairs of pixels, for example.

Abstract: The pointing device is used in connection with a computer system, and has a sensor for sensing data representing a displacement information in at least two spatial coordinates. The device is capable of toggling between a first and a second mode of operation, and also adjusting the displacement information referring to a first of the two spatial coordinates (i.e. first displacement information) in view of a second of the two spatial coordinates (i.e. second displacement information) when the second mode of operation is activated.

Abstract: An interpolation filter for interpolating a digital signal includes a cascade of template filters, each having an identical template transfer function A(z), which is arranged to receive and filter an input sequence representing the digital signal sampled at an input sampling rate. Ancillary circuitry is coupled to the cascade so as to produce first and second phase outputs. A multiplexer is arranged to multiplex the phase outputs in order to generate an output sequence having an output sampling rate equal to twice the input sampling rate.

Abstract: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.

Abstract: An image sensor may have a pixel array and an imaging lens for forming an image on the pixel array. The sensor may also include a pixel readout unit for enabling individual pixel values to be readout. The sensor may further include a pixel selection unit wherein at least one pixel sub-array is selected according to the pixel values readout and the at least one sub-array is used for reading the image.

Abstract: A digital filter is provided that may replace a center pixel with the nearest-valued opposing average. The filter may reduce the amplitude of a defective pixel couplet by at least 50%, and may structure noise into linear artifacts.

Abstract: A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring whether the initiator or the distributed routing network is responsible for ordering responses to requests issued by the initiator port and defining the maximum number of requests that are permitted to be outstanding at the same time. The initiator port is further configured to define whether a delay stage is required in said initiator port. The distributed routing network is defined by the number of routing resources between the initiator and the target, an arbitration method for arbitrating between requests and an association between the routing resources and the targets.

Abstract: A detection apparatus is for a computer to detect the presence or absence of a computer user. The absence of a user can trigger a computer display to power down, while the detected presence of a user can trigger the display to power back up, and, optionally, require a log in. The detection apparatus may operate automatically and thus may provide a reliable way of saving power and/or ensuring security of computer data.

Abstract: A method of mounting an electronic component having at least one contact extending across a part of its undersurface may include providing a support smaller in area than the undersurface of the component and having a contact pad for connection to the contact. The contact pad may have a first portion extending across an upper surface of the support adjacent one edge and a second portion extending from the edge across a side surface of the support. The method may also include positioning the electronic component and the support with the undersurface of the component adjacent the upper surface of the support. This is done so that the first portion of the contact pad is aligned with and spaced apart from a first portion of the contact, and the second portion of the contact pad is aligned with and disposed inwardly of a second portion of the contact.

Abstract: A method for manufacturing an image sensor including an array of pixels and an imaging lens exit pupil for focusing rays of light onto the array of pixels is provided. Each pixel includes a light sensitive region and at least one optical element associated therewith. The method includes positioning the at least one optical element for each pixel relative to its associated light sensitive region based upon a range of acceptable angles of incidence for the rays of light from the imaging lens exit pupil.

Abstract: A method for image compression of a set of image data includes performing a quantization operation on the image data. The quantization operation may include controlling a compression factor by applying a scaled quantization level obtained by multiplying a first quantization level by a gain factor. The gain factor may be updated as a function of a bit per pixel value of a compressed image. The update operation may include an iterative procedure including at least one iteration step that provides for updating a current gain factor as a function of a previous gain used for performing a previous compression step and as a function of a ratio of the bit per pixel value of the compressed image at the previous compression step to a target bit per pixel value. The method may be used in Joint Photographic Experts Group (JPEG) image processing and digital still cameras.

Abstract: A light monitor includes a single semiconductor substrate. A light to frequency (LTF) converter is on the single semiconductor substrate, a threshold comparator is on the single semiconductor substrate and coupled to an output of the light to frequency converter, and a light intensity calculator is on the single semiconductor substrate and coupled to an output of the threshold comparator.