Patents Assigned to STMicroelectronics Pte Ltd
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Publication number: 20130248887Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.Type: ApplicationFiled: March 18, 2013Publication date: September 26, 2013Applicants: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (GRENOBLE 2) SASInventors: Romain Coffy, Eric Saugier, Hk Looi, Norbert Chevrier
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Patent number: 8535980Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 ?m or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.Type: GrantFiled: December 23, 2010Date of Patent: September 17, 2013Assignee: STMicroelectronics Pte Ltd.Inventors: Puay Gek Chua, Yonggang Jin
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Patent number: 8526214Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.Type: GrantFiled: November 15, 2011Date of Patent: September 3, 2013Assignee: STMicroelectronics Pte Ltd.Inventor: Olivier Le Neel
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Patent number: 8502367Abstract: An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking.Type: GrantFiled: September 29, 2010Date of Patent: August 6, 2013Assignee: STMicroelectronics Pte Ltd.Inventor: Jing-En Luan
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Patent number: 8502394Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.Type: GrantFiled: December 31, 2009Date of Patent: August 6, 2013Assignee: STMicroelectronics Pte Ltd.Inventor: Kim-Yong Goh
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Patent number: 8502556Abstract: A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.Type: GrantFiled: December 30, 2011Date of Patent: August 6, 2013Assignees: STMicroelectronics Asia Pacific Pte Ltd, STMicroelectronics Pte LtdInventors: Yann Desprez-Le-Goarant, Jingfeng Gong
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Patent number: 8497587Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.Type: GrantFiled: December 30, 2009Date of Patent: July 30, 2013Assignee: STMicroelectronics Pte Ltd.Inventor: Yiyi Ma
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Patent number: 8492181Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.Type: GrantFiled: December 22, 2011Date of Patent: July 23, 2013Assignee: STMicroelectronics Pte Ltd.Inventors: Anandan Ramasamy, KahWee Gan, Hk Looi, David Gani
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Publication number: 20130168899Abstract: A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. The runner system includes a runner with a plurality of reservoirs along its length, with a gate extending from each of the reservoirs to one of the cavities. A particle trap is positioned on the bottom of the runner between a sprue and a first one of the reservoirs, to capture contaminating particles in a flow of molding compound before the particles enter any of the reservoirs. The particle trap can be, for example, a notch or a channel extending transversely across the bottom of the runner, or a dummy reservoir upstream of the first of the plurality of reservoirs.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PTE LTD.Inventors: Jerome Teysseyre, Glenn de los Reyes
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Publication number: 20130171816Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PTE LTD.Inventor: Yonggang Jin
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Publication number: 20130169312Abstract: A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Applicants: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS ASIA PACIFIC PTE LTDInventors: Yann Desprez-Le-Goarant, Jingfeng Gong
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Publication number: 20130168355Abstract: Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMicroelectronics Pte Ltd.Inventors: Ying Yu, Tien Choy Loh, Shian Yeu Kam
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Publication number: 20130170164Abstract: On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PTE LTD.Inventors: Jing-En Luan, Hk Looi
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Publication number: 20130170169Abstract: An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Applicant: STMICROELECTRONICS PTE LTDInventors: KahWee GAN, Yaohuang HUANG
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Publication number: 20130168858Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.Type: ApplicationFiled: December 20, 2012Publication date: July 4, 2013Applicant: STMICROELECTRONICS PTE LTD.Inventor: STMicroelectronics Pte Ltd.
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Publication number: 20130168815Abstract: The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off.Type: ApplicationFiled: December 30, 2011Publication date: July 4, 2013Applicant: STMicroelectronics Pte Ltd.Inventors: Olivier Le Neel, Ravi Shankar
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Publication number: 20130168377Abstract: An adapter is provided for fluidly coupling a process chamber, such as a diffusion furnace or a process tube, and a fluid source, such as a torch chamber or combustion chamber, of a system for processing semiconductor material. The process tube and the torch chamber include joint segments that can engage directly together to fluidly couple the torch chamber to the process tube for introducing a fluid, such as an oxidizing gas or vapor, into the process tube. The process chamber and the torch chamber are formed of materials having different rates of thermal expansion. The adapter is configured to couple the joint segments of the torch chamber and the process tube while accommodating the differences in thermal expansion between the materials. The adapter may be formed of quartz to couple a quartz torch chamber with a silicon carbide process tube.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: STMicroelectronics Pte Ltd.Inventors: Ying Shun Liang, Samuel Gordon McKee
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Publication number: 20130164867Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: STMicroelectronics Pte Ltd.Inventors: Anandan Ramasamy, KahWee Gan, Hk Looi, David Gani
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Patent number: 8466997Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals.Type: GrantFiled: December 31, 2009Date of Patent: June 18, 2013Assignee: STMicroelectronics PTE Ltd.Inventors: Kim-Yong Goh, Jing-En Luan
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Publication number: 20130147052Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: STMICROELECTRONICS PTE LTD.Inventors: Xueren Zhang, Kim-Yong Goh