Patents Assigned to STMicroelectronics Pte Ltd
  • Publication number: 20150035133
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Wing Shenq Wong
  • Publication number: 20150028187
    Abstract: An image sensor device may include a mounting substrate having an IC-receiving cavity therein and a filter-receiving opening aligned with the IC-receiving cavity, an image sensor integrated circuit (IC) within the IC-receiving cavity and having an image sensing area aligned with the filter-receiving opening, and an adhesive bead on the image sensor IC surrounding the image sensing area. Furthermore, an infrared (IR) filter may be within the filter-receiving opening and have peripheral portions contacting the adhesive bead.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: STMICROELECTRONICS PTE LTD
    Inventors: Yonggang JIN, Bin-Hong HUANG
  • Patent number: 8937008
    Abstract: A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 20, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Yonggang Jin
  • Patent number: 8937774
    Abstract: A method comprises depositing an optical filter layer on a glass wafer, then cutting the wafer into dice. The dice are positioned on a carrier and encapsulated in a molding compound to form a reconstituted wafer, and the wafer is back-ground and polished. Lens faces are positioned on opposing surfaces of the glass dice and spacers are positioned on one side of the wafer. The wafer is then cut into lens modules, each having two side-by-side lenses with an opaque molding compound barrier between. The individual modules are attached to devices that require dual lenses, such as, e.g., proximity sensors that use a light source and a light receiver or detector.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: January 20, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Laurent Herard
  • Patent number: 8934052
    Abstract: A low profile chip scale module and method of making of the same. The low profile chip scale module includes embedded SMD and integrated EM shielding. An adhesive layer is arranged on a substrate, e.g., chip carrier. Dies and SMDs are arranged on the adhesive layer. An etched frame and molding is attached to the substrate. Inputs/outputs (I/O) are formed and the substrate is coated with a dielectric material. Metal lines and connections among bond pads are formed and another layer of dielectric material is applied as a protective layer. The substrate is cut into various predetermined sizes and a lens is attached to form the chip scale module.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: January 13, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Jing-En Luan
  • Patent number: 8922013
    Abstract: An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 30, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: How Yuan Hwang, Kah Wee Gan
  • Patent number: 8916481
    Abstract: A process for manufacturing a 3D or PoP semiconductor package includes forming a redistribution layer on a reconstituted wafer, then laser drilling a plurality of apertures in the reconstituted wafer, extending from an outer surface of the reconstituted wafer to intersect electrical traces in the first redistribution layer. A solder ball is then positioned adjacent to an opening of each of the apertures. The solder balls are melted and allowed to fill the apertures, making contact with the respective electrical traces and forming a plurality of solder columns. The outer surface of the reconstituted wafer is then planarized, and a second redistribution layer is formed on the planarized surface. The solder columns serve as through-vias, electrically coupling the first and second redistribution layers on opposite sides of the reconstituted wafer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kah Wee Gan, Yaohuang Huang, Yonggang Jin
  • Patent number: 8912653
    Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kah Wee Gan, Yonggang Jin, Anandan Ramasamy, Yun Liu
  • Patent number: 8907465
    Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Kim-Yong Goh, Yiyi Ma, Wei Zhen Goh
  • Patent number: 8890269
    Abstract: A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Jing-En Luan
  • Patent number: 8885390
    Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Olivier Le Neel
  • Patent number: 8884422
    Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Kim-Yong Goh, Jing-En Luan
  • Patent number: 8860207
    Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics Pte Ltd, STMicroelectronics Grenoble 2 SAS
    Inventors: Yonggang Jin, Romain Coffy, Jerome Teysseyre
  • Patent number: 8860152
    Abstract: A integrated circuit die includes a chemical sensor, a thermal sensor, and a humidity sensor formed therein. The chemical sensor, thermal sensor, and humidity sensor include electrodes formed in a passivation layer of the integrated circuit die. The integrated circuit die further includes transistors formed in a monocrystaline semiconductor layer.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Suman Cherian, Olivier Le Neel
  • Patent number: 8860228
    Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics Pte. Ltd.
    Inventors: Yonggang Jin, Yun Liu, Yaohuang Huang
  • Publication number: 20140291677
    Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Olivier Le Neel, Ravi Shankar, Suman Cherian, Calvin Leung, Tien-Choy Loh, Shian-Yeu Kam
  • Publication number: 20140291812
    Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
  • Publication number: 20140292317
    Abstract: A miniature oxygen sensor makes use of paramagnetic properties of oxygen gas to provide a fast response time, low power consumption, improved accuracy and sensitivity, and superior durability. The miniature oxygen sensor disclosed maintains a sample of ambient air within a micro-channel formed in a semiconductor substrate. O2 molecules segregate in response to an applied magnetic field, thereby establishing a measureable Hall voltage. Oxygen present in the sample of ambient air can be deduced from a change in Hall voltage with variation in the applied magnetic field. The magnetic field can be applied either by an external magnet or by a thin film magnet integrated into a gas sensing cavity within the micro-channel. A differential sensor further includes a reference element containing an unmagnetized control sample. The miniature oxygen sensor is suitable for use as a real-time air quality monitor in consumer products such as smart phones.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Olivier Le Neel, Ravi Shankar
  • Publication number: 20140293558
    Abstract: A lens mount is attached to a circuit board and covers electrical components on the circuit board. An electrically insulating device is positioned between the lens mount and the circuit board. The circuit board includes a grounding pad adjacent the electrically insulating device. The lens mount includes an aperture aligned with the grounding pad and the electrically insulating device. A conductive glue is dispensed into the aperture to electrically ground the lens mount to the grounding pad. The electrically insulating device seals the conductive glue from the electrical components. A method of grounding a lens mount to a circuit board is provided.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Wee Chin Judy Lim
  • Publication number: 20140291867
    Abstract: A semiconductor package includes an RFID chip positioned between a first die and a second die attached to a support substrate. The RFID chip is free of electrical connections to the dice and the support substrate. The RFID chip is sized to correspond to an interposer board. Data pertaining to operating characteristics of the dice are stored to and read from the RFID chip during back-end processing to determine abnormalities and improve yield. Said data may be stored to a database corresponding to the RFID chip in the package. A method of making a semiconductor package having an RFID chip positioned between dice is provided. The package is traceable by customers via the data stored to the RFID chip and the database.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Yohanes Bintang