Patents Assigned to STMicroelectronics Pvt. Ltd.
  • Patent number: 9160336
    Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 13, 2015
    Assignee: STMICROELECTRONICS PVT LTD
    Inventors: Abhishek Jain, Chittoor Parthasarathy, Kallol Chatterjee
  • Patent number: 8963053
    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 24, 2015
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Nishu Kohli, Mudit Bhargava, Shishir Kumar
  • Publication number: 20140340133
    Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.
    Type: Application
    Filed: May 13, 2014
    Publication date: November 20, 2014
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics Pvt. Ltd.
    Inventors: Gilles Gasiot, Sylvain Clerc, Junaid Yousuf, Maximilien Glorieux
  • Patent number: 8805081
    Abstract: The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions (310, 312, 314) of a first search window (108); generating a cumulative score based on results of said one or more tests on said plurality of sub-regions; comparing said cumulative score with a threshold value; and based on said comparison, selectively performing one or more of said tests of said test sequence on at least one further sub-region of said first search window, said at least one further sub-region at least partially overlapping each of said plurality of sub-regions.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: August 12, 2014
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics PVT Ltd
    Inventors: Ludovic Chotard, Michel Sanches, Vitor Schwambach, Mahesh Chandra
  • Patent number: 8793228
    Abstract: A system includes a storage subsystem having a data area and a header area. The data area is for storing contents of at least one data file, and the header area is for storing access parameters and status information for accessing each data file individually. The data area and the header area define a storage area in the storage subsystem. Multiple files are efficiently managed based on utilization of the storage area in the storage subsystem.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Vipin Bansal, Deepak Naik, Raunaque Quaiser, Alok Kumar Mittal
  • Publication number: 20140184912
    Abstract: A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map.
    Type: Application
    Filed: November 26, 2013
    Publication date: July 3, 2014
    Applicant: STMicroelectronics Pvt Ltd.
    Inventor: RajeshSidana Omprakash
  • Publication number: 20140036564
    Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 6, 2014
    Applicants: STMicroelectronics PVT LTD, STMicroelectronics S.r.l.
    Inventors: Fabio DE SANTIS, Marco PASOTTI, Abhishek LAL
  • Publication number: 20140015577
    Abstract: A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Anand KUMAR, Pradeep DHADDA
  • Publication number: 20140013177
    Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 9, 2014
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventor: Parul Bansal
  • Publication number: 20140009633
    Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: STMICROELECTRONICS PVT. LTD
    Inventors: Sanjeev CHOPRA, Hiten ADVANI
  • Publication number: 20130308397
    Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventor: Nishu Kohli
  • Publication number: 20130308399
    Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventor: Nishu Kohli
  • Publication number: 20130205587
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 15, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventor: STMicroelectronics Pvt. Ltd.
  • Publication number: 20130202031
    Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 8, 2013
    Applicants: STMICROELECTRONICS SRL, STMICROELECTRONICS PVT. LTD.
    Inventors: STMICROELECTRONICS PVT. LTD., STMICROELECTRONICS SRL
  • Patent number: 8497795
    Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: July 30, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics Pvt. Ltd., STMicroelectronics (Canada) Inc., STMicroelectronics S.r.l.
    Inventors: Stéphane Le Tual, Pratap Narayan Singh, Oleksiy Zabroda, Nicola Vannucci
  • Publication number: 20130181754
    Abstract: In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.
    Type: Application
    Filed: March 4, 2013
    Publication date: July 18, 2013
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventor: STMicroelectronics Pvt. Ltd.
  • Publication number: 20130170306
    Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Navneet GUPTA, Prashant DUBEY, ShaileshKumar PATHAK, Kaushik SAHA, Ashish KUMAR, R Sai KRISHNA
  • Publication number: 20130170289
    Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
  • Publication number: 20130169360
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Navneet GUPTA, Prashant DUBEY, Kaushik SAHA, AtulKumar KASHYAP
  • Publication number: 20130170275
    Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
    Type: Application
    Filed: August 22, 2012
    Publication date: July 4, 2013
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Shishir Kumar, Dibya Dipti, Pierre Malinge