Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

Abstract: A system includes a storage subsystem having a data area and a header area. The data area is for storing contents of at least one data file, and the header area is for storing access parameters and status information for accessing each data file individually. The data area and the header area define a storage area in the storage subsystem. Multiple files are efficiently managed based on utilization of the storage area in the storage subsystem.

Abstract: A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF.

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract: A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.

Abstract: A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage.

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu

Abstract: In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.

Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.

Abstract: A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode.

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.