Patents Assigned to STMicroelectronics Pvt. Ltd.
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Publication number: 20120169438Abstract: An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Applicant: STMICROELECTRONICS PVT LTD.Inventors: Tapas NANDY, Nitin GUPTA
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Publication number: 20120170391Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Dhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
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Publication number: 20120170587Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.Type: ApplicationFiled: December 31, 2010Publication date: July 5, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Gaurav MATHUR, Pratik DAMLE
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Publication number: 20120168934Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: STMicroelectronics Pvt Ltd.Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
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Publication number: 20120166856Abstract: Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.Type: ApplicationFiled: June 29, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Ankur BAL, Anupam JAIN
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Publication number: 20120166860Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.Type: ApplicationFiled: June 2, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTDInventors: Shray Khullar, Swapnil Bahl
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Publication number: 20120163064Abstract: A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair.Type: ApplicationFiled: July 8, 2011Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Nitin Jain, Piyush Jain
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Publication number: 20120166131Abstract: Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.Type: ApplicationFiled: June 29, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventor: V. SRINIVASAN
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Publication number: 20120161823Abstract: Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.Type: ApplicationFiled: July 7, 2011Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventor: Nitin Gupta
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Publication number: 20120166900Abstract: A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit.Type: ApplicationFiled: June 17, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventor: Ajay Kumar Dimri
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Publication number: 20120163110Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rakesh Kumar Sinha, Dhori Kedar Janardan, Sachin Gulyani
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Publication number: 20120163063Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.Type: ApplicationFiled: June 24, 2011Publication date: June 28, 2012Applicant: STMicroelectronics Pvt Ltd.Inventor: Jitendra DASANI
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Publication number: 20120161883Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.Type: ApplicationFiled: July 6, 2011Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventor: Prashant Dubey
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Publication number: 20120161848Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventor: Rajeev Jain
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Publication number: 20120161888Abstract: An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications.Type: ApplicationFiled: June 30, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Abhirup LAHIRI, Anurag TIWARI
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Publication number: 20120158339Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Nitin Chawla, Kallol Chatterjee, Chittoor Parthasarathy
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Publication number: 20120140582Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Applicant: STMicroelectronics PVT. LTD.Inventors: Siddharth GUPTA, Nitin Jain, Anand Mishra
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Publication number: 20120139771Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second pluType: ApplicationFiled: June 22, 2011Publication date: June 7, 2012Applicants: STMicroelectronics S.A., STMicroelectronics S.r.l., STMicroelectronics (Canada) Inc., STMicroelectronics Pvt. Ltd.Inventors: Stéphane Le Tual, Pratap Narayan Singh, Oleksiy Zabroda, Nicola Vannucci
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Publication number: 20120137188Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Tanmoy Roy, Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria
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Publication number: 20120099832Abstract: A portable video player includes: a data input coupled to a memory module to store at least one video file, a video decoder coupled to the memory module via a memory interface to decode the video file, and a video interface connector to output to a display the decoded video file.Type: ApplicationFiled: October 20, 2010Publication date: April 26, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventors: Nitin Gupta, Tapas Nandy