Abstract: In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing.

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract: In accordance with an embodiment, a reference voltage generator includes a first current generator and a second current generator. The first current generator is configured to produce a first current proportional to a current through a first diode connected in series with the first resistance coupled between a first voltage and a second voltage, such that the first current is produced according to a first proportionality constant. The second current generator is configured to produce a second current proportional to a current through a second diode connected in series with the second resistance coupled between the first voltage and the second voltage, such that the second current is produced according to a second proportionality constant. The reference voltage generator further includes a reference resistor coupled to the first and second current generators and to and output of the reference voltage generator.

Abstract: A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract: An embodiment of a multiplying digital-to-analog converter (MDAC), an embodiment of a method for converting a digital signal to an analog signal, an embodiment of a pipelined analog-to-digital converter (ADC), and a method of converting an analog signal to a digital signal in a plurality of cascading stages.

Abstract: A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value.

Abstract: A video decoder includes an adaptive comber to generate a combed video image, and the adaptive comber selectively combs using 2D combing, frame combing, and field combing.

Abstract: A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map.

Abstract: A battery pack management system provides information such as remaining capacity and/or run time to empty for a battery. A time taken for a battery voltage to drop a threshold amount is measured and used to determine a remaining capacity of the battery. The time may be associated with a temperature and current of the battery. The remaining capacity of a battery is calculated by monitoring a discharge of the battery. For example, current drawn from the battery is monitored over a period of time and an initial amount by which the battery has been discharged is calculated. Compensation of this initial amount is carried out in order to take into account factors such as temperature, self-discharge rate and age of the battery.

Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: A video processor includes a spatio-temporal noise reduction controller to determine current and previous image edge slopes and adaptively control a spatio-temporal noise reduction processor to blend current and previous images dependent on the current and previous image edge slope values.

Abstract: A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.