Abstract: An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.

Abstract: The present description concerns a method of implementation of an NFC transaction between a mobile terminal and a distant module. The terminal includes a processor hosting an application establishing the NFC transaction, a near-field communication module, and a secure element distinct from the processor. The method includes at least the following successive steps: (a) the near-field communication module ciphers first data sent by the distant module by using a first key supplied by the secure element and (b) the first application deciphers the first data by using a second key supplied by the secure elements.

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor device includes forming a first front layer and a first rear layer of a first material respectively on a front main face and a rear main face of a semiconductor substrate wafer; forming a first plurality of trenches and a second plurality of trenches respectively in a surface of the first front layer and in a surface of the first rear layer; forming a second front layer of a second material on the first front layer, where the second front layer extends over the first front layer, in the first plurality of trenches, and between the first plurality of trenches on the surface of the first front layer; and forming a second rear layer of the second material on the surface of the first rear layer, wherein the second rear layer extends over the first rear layer, in the second plurality of trenches, and between the second plurality of trenches on the surface of the first rear layer.

Abstract: A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.

Abstract: One embodiment provides a digital-to-analog converter that includes an output amplifier configured to be powered with a controllable power supply voltage and a ground reference voltage. The output amplifier is configured to generate an analog output signal having a dynamic range centered on a common-mode voltage. The output amplifier includes a common-mode adaptation circuit configured to position a level of the common-mode voltage at a level located in a middle portion of an interval of voltages located between the power supply voltage and the ground reference voltage, according to an effective level of the power supply voltage.

Abstract: The present disclosure concerns a photodiode including at least one memory area, each memory area including at least two charge storage regions.

Abstract: A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.

Abstract: A DC-DC boost converter includes an input receiving an input voltage and an output producing an output voltage. A switching stage is formed by a low-side transistor arranged between a switching node and a ground node, and a high-side transistor arranged between the switching node and the output. The high-side transistor includes a body diode having an anode coupled to the switching node and a cathode coupled to the output. The converter is controlled in an asynchronous operation mode where the low-side transistor is driven alternately to a conductive state and a non-conductive state, and the high-side transistor is driven steadily to a non-conductive state. A variable load circuit is selectively coupled between the two output terminals when the converter is in the asynchronous operation mode in order to sink a load current having a value that is a function of a value of the input voltage.

Abstract: An electronic device receives a software module of a first application, where the software includes comprising a public key associated with the first application. A cryptographic circuit of the electronic device generates an encryption key based on a secret key of the electronic device and on one of: the public key or and an identification value derived from the public key. The cryptographic circuit then generates one or more protected data items by application of a cryptographic operation to one or more first data items associated with the first application and based on the encryption key. The one or more protected data items are then stored in a first portion of a memory of the electronic device.

Abstract: A laminated structure includes metal tracks. In a method for making, a first layer of a first dielectric material is deposited on a substrate. One or more openings are then made in the first layer. A second dielectric material is then deposited within the openings formed in the first layer. The second dielectric material has dielectric properties distinct from the dielectric properties of the first dielectric material.

Abstract: An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

Abstract: The present disclosure is directed to devices and methods for performing context recognition. The context recognition detects whether the device is in a lid closed mode or a tablet mode. The context recognition is configured to handle exception cases including a first exception case in which context recognition is started while in an upright mode, and a second exception case in which context recognition is started while the device is in a lid closed mode or a tablet mode.

Abstract: A ranging system includes a source of polarized light generating an emitted light beam, and a metasurface optical element (MOE) positioned to receive the emitted light beam from the source of polarized light and configured to transform the emitted light beam from having linear polarization to having circular polarization of a first handedness. An optical element is positioned to receive the emitted light beam from the MOE and direct the emitted light beam toward a target. The emitted light beam reflects off the target and returns as a reflected light beam to be passed by the optical element back through the MOE as having circular polarization of a second handedness opposite to the first handedness. The MOE is positioned to receive the reflected light beam from the optical element and configured to transform the reflected light beam back to having the linear polarization. A sensor senses the reflected light beam.

Abstract: An integrated circuit includes lateral isolation regions delimiting active regions in a semiconductor substrate. A trench is etched extending vertically in depth into the semiconductor substrate and intended to pass through the lateral isolation regions and the active regions. The formation of the lateral isolation regions includes forming sacrificial lateral isolation regions positioned at a location of the etching of the trench which passes through the active regions.

Abstract: HEMT device comprising: a heterostructure comprising a channel layer and a barrier layer extending, along a first axis, onto the channel layer; a dielectric protection layer of dielectric material, extending along the first axis onto the barrier layer; and a gate region extending along the first axis onto the dielectric protection layer, wherein the dielectric protection layer has, along the first axis, a thickness lower than 10 nm.

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

Abstract: An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.

Abstract: According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.