Abstract: One or more semiconductor dice are arranged on a substrate. The semiconductor die or dice have a first surface adjacent the substrate and a second surface facing away from the substrate. Laser-induced forward transfer (LIFT) processing is applied to the semiconductor die or dice to form fiducial markers on the second surface of the semiconductor die or dice. Laser direct structuring (LDS) material is molded onto the substrate. The fiducial markers on the second surface of the semiconductor die or dice are optically detectable at the surface of the LDS material. Laser beam processing is applied to the molded LDS material at spatial positions located as a function of the optically detected fiducial markers to provide electrically conductive formations for the semiconductor die or dice.

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.

Abstract: In accordance with an embodiment a method includes: receiving a slow down command to slow down a speed of a voice coil motor (VCM) in a hard disk drive; in response to receiving the slow down command, operating the VCM in a discontinuous mode by switching on and off a current through the VCM with a duty-cycle, wherein operating the VCM in the discontinuous mode reduces the speed of the VCM; sensing the speed of the VCM while operating the VCM in the discontinuous mode; and varying the duty-cycle of the switching on and off the current through the VCM as a function of the sensed speed of the VCM operated in the discontinuous mode, wherein varying the duty-cycle comprises reducing the duty-cycle in response to a reduction of the sensed VCM speed.

Abstract: A circuit can be used for reading out a light sensor. The circuit includes an operational amplifier. A first capacitor has a first electrode coupled to an inverting input of the operational amplifier and a second electrode coupled to a non-inverting output of the operational amplifier. A compensation circuit is coupled between the operational amplifier and the first capacitor. A preset circuit has an input coupled to a first voltage node and an output coupled to the first capacitor. The first voltage node configured to carry a first voltage equal to a preset voltage multiplied by a coefficient.

Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

Abstract: An electronic device includes—a semiconductor substrate having selection transistors arranged therein and a first interconnection stack including at least one level including first and second insulating layers having conductive tracks and first conductive vias defined therein. The electronic device includes a third insulating layer on the first stack and a second interconnection stack including at least one level including first and second insulating layers. The electronic device includes a plurality of memory cells arranged in the third insulating layer and at least one second conductive via extending through the entire height of the third insulating layer.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: In an embodiment, a method includes: receiving a first plurality of digital codes from a time-to-digital converter (TDC); generating a coarse histogram from the first plurality of digital codes; detecting a peak coarse bin from the plurality of coarse bins; after receiving the first plurality of digital codes, receiving a second plurality of digital codes from the TDC; and generating a fine histogram from the second plurality of digital codes based on the detected peak coarse bin, where a fine histogram depth range is narrower than a coarse histogram depth range, where a lowest fine histogram depth is lower or equal to a lowest coarse peak depth, and where a highest fine histogram depth is higher or equal to a highest coarse peak depth.

Abstract: A device and method of manufacturing a device based on heterostructure, including a work body, is provided having a wafer and an epitaxial multilayer that extends on the wafer along a direction from a front surface of the wafer up to an upper surface. To form an active area, a conduction region of conductive material is formed on the epitaxial multilayer. To form a contact region for biasing the first conduction region: a front trench is formed in the work body starting from the upper surface towards the back surface of the wafer, up to a contact surface; a conductive region is formed inside the front trench, on the contact surface, and in electrical contact with the first conduction region; a back trench is formed in the work body starting from the back surface towards the upper surface up to the contact surface; and a back metallization layer is formed on the back surface of the wafer and inside the back trench, on the contact surface.

Abstract: A first input node and a second input node are coupled to a sensing circuit element. A first transistor of a pair of differential transistors has a current flow path with a first transistor node coupled to the first input node to receive a current sensing signal and a second transistor node. A second transistor of the pair of differential transistors has a current flow path with a third transistor node coupled to the second input node to receive a current sensing signal and a fourth transistor node. An auxiliary amplifier circuit has a first auxiliary input node coupled to the second transistor node and a second auxiliary input node coupled to the fourth transistor node. An output node of the auxiliary amplifier circuit generates a control signal applied to a common control node of the pair of differential transistors.

Abstract: An electronic device, such as a smart card, includes a first secure element configured to implement a transaction in response to received data, and a second secure element configured to receive the same data as the first secure element and perform an operation which can control another electronic circuit.

Abstract: A foldable electronic device includes a first lid and a second lid rotatably coupled together by a hinge. A first inertial measurement unit (IMU) is implemented in the first lid and generates first sensor data. A second IMU is implemented in the second lid and generates second sensor data. A sensor processing unit detects the rotation angle between the first and second lids and generates rotated second sensor data by adjusting the second sensor data based on the rotation angle. The sensor processing unit generates combined sensor data by combining the first sensor data with the rotated second sensor data. The combined sensor data is more accurate than either the first sensor data or the second sensor data.

Abstract: The present description concerns an electronic circuit manufacturing method comprising, in the order, forming an opening in a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the opening positioned between the first surface and the second surface and forming an electrically-conductive pad, the electrically-conductive pad including a first portion positioned over the first surface and a second portion covering the flanks of the opening and delimiting a gap in the opening, and depositing a first layer covering the electrically-conductive pad and filling the gap, the first layer containing a first resin, the first resin being non-photosensitive, and crosslinking the first resin in the first layer, and chemically etching by plasma the first layer to delimit a first block of the first resin in the gap, and depositing a first protection layer on the first block.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: A voltage conversion system provides gain and offset trimming for generating a controlled output voltage. The system includes a digital-to-analog converter (DAC) that generates a reference voltage based on an input code, and a voltage converter that converts an input voltage to an output voltage based on the reference voltage. A first adjustable reference circuit provides a first reference signal to the DAC and a second adjustable reference circuit provides a second reference signal to the DAC. Control circuitry adjusts the first adjustable reference circuit to perform gain trimming of the output voltage and adjusts the second adjustable reference circuit to perform offset trimming of the output voltage. A calibration procedure includes adjusting for both gain and offset, with a two-step approach for positive offset conditions—first incrementing the input code to create a negative offset, then performing offset trimming.

Abstract: The present description concerns a bus error management method, wherein one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge, are stored, and wherein in the presence of a bus error sent by the functional unit: one or a plurality of second characteristics linked to said error are stored; the bridge generates a first interrupt that it transmits with said first and second characteristics to a management unit; and the management unit generates at least one second interrupt intended for a processing unit as a function of the first and/or second characteristics.

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.