Abstract: Provided is a module for monitoring instructions of a microcontroller. The module is adapted to receive instructions that are received at an input terminal of the microcontroller or that are being processed by a code pointer of the microcontroller. The module verifies the instructions received on the input terminal of the microcontroller or that are being processed by the code pointer of the microcontroller.

Abstract: An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.

Abstract: An electrostatic discharge protection circuit protects a first transistor. The circuit includes N diodes in series between conduction terminals of the first transistor. A second transistor and third transistor are connected in series between the conduction terminals of the first transistor. A control terminal of the third transistor is coupled to an anode of the N diodes. A first inverter couples the control terminals of the first and second transistors. A fourth transistor is connected in parallel with the first transistor. A control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. A capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.

Abstract: A substrate includes electrically conductive leads arranged laterally of a die mounting location. A semiconductor die is mounted at the die mounting location. An electrical coupling member electrically couples the semiconductor die with one or more electrically conductive leads. The electrical coupling member includes one or more electrically conductive pads having first and second electrically conductive ribbons protruding therefrom. The first and second electrically conductive ribbons have proximal ends at the electrically conductive pad and distal ends away from the electrically conductive pad. The distal ends of the first and second electrically conductive ribbons are electrically coupled to the semiconductor die and an electrically conductive lead, respectively, to provide electrical coupling therebetween.

Abstract: A method of facilitating live feedback on code generation includes generating first source code based on user configuration, presenting the generated first source code in a live preview user interface, and obtaining a change to the user configuration. The method also includes, responsive to the obtaining of the first change: generating second source code based on the first change; computing differences between the second source code and the first source code; and presenting the second source code in the live preview user interface by: visually signaling a correspondence between the first change and portions of the second source code that are associated with the differences; and visually distinguishing the portions of the second source code from other portions of the second source code.

Abstract: A process forms a high electron mobility transistor (HEMT) device with a recessed gate without damaging sensitive areas of the HEMT device. The process utilizes a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. The channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. The result is that the channel layer and the barrier layer growth around the passivation structure. The passivation structure is then removed, effectively leaving a recess in the channel layer. The gate electrode is then formed in the recess.

Abstract: A power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. A current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. A voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a VDS sense current. A safe operating area (SOA) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the VDS sense current, the SOA shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. A timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. An output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. The control signal is modified in response to assertion of the flag.

Abstract: A first switch couples an input node receiving a main control signal for a main switching stage of a multi-phase converter to an output node delivering a secondary control signal for a secondary switching stage following actuation of the secondary switching stage. A second switch couples the output node to a capacitor during a time period of actuation/deactuation of the secondary switching stage. Current is sourced to the capacitor during the actuation time period or sunk from the capacitor during the deactuation time period. The sourced or sunk current may be generated proportional to the main control signal.

Abstract: A device includes a memory, a first firmware copy of the device stored in a first position of the memory and a second firmware copy of the device stored in a second position of the memory, where each of the first firmware copy and the second firmware copy includes instructions, when executed by the device, perform an operation of the device; and a first delta copy associated with the first firmware copy. The first delta copy includes instructions that differ from the first firmware copy when executed at the first position and are the same when executed at the second position. The device is configured to receive the first delta copy from an external system and store the first delta copy in the memory.

Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

Abstract: In an embodiment a device includes a supply node configured to receive a supply voltage, an output node configured to provide an output voltage, a plurality of switching stages coupled to the supply node and to the output node, a sensing circuit coupled to the supply node and configured to provide at least one sensing signal based on the supply voltage and a driver circuit coupled to the sensing circuit and to the plurality of switching stages, wherein the driver circuit is configured to provide the drive signal based on at least one sensing signal exceeding or failing to exceed at least one reference voltage level and to selectively bypass a selected number of the plurality of switching stages based on the drive signal thereby varying an output voltage level at the output node.

Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.

Abstract: A microelectromechanical mirror device has, in a die of semiconductor material: a fixed structure defining a cavity; a tiltable structure carrying a reflecting region elastically suspended above the cavity; at least a first pair of driving arms coupled to the tiltable structure and carrying respective piezoelectric material regions which may be biased to cause a rotation thereof around at least one rotation axis; elastic suspension elements coupling the tiltable structure elastically to the fixed structure and which are stiff with respect to movements out of the horizontal plane and yielding with respect to torsion; and a piezoresistive sensor configured to provide a detection signal indicative of the rotation of the tiltable structure. At least one test structure is integrated in the die to provide a calibration signal indicative of a sensitivity variation of the piezoresistive sensor in order to calibrate the detection signal.

Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

Abstract: Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.