Abstract: A process for manufacturing a MEMS piezoelectric device includes: forming a membrane at a first surface of wafer of semiconductor material further having a second surface (the first and second surfaces being opposite along a vertical axis and extending parallel to a horizontal plane formed by first and second horizontal axes); forming a cavity within the wafer so that the membrane is suspended above the cavity; forming a piezoelectric material layer above a first surface of the membrane; forming an electrode arrangement in contact with the piezoelectric material layer; and forming a proof mass coupled to a second surface of the membrane opposite to the first surface along the vertical axis. The proof mass deforms the membrane in response to environmental mechanical vibrations. Forming the proof mass includes forming a connection element at a central position between the membrane and the proof mass in the direction of the vertical axis.

Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

Abstract: A embodiment method, for linearizing a transmission signal resulting from a quadrature amplitude modulation of an analog baseband signal and a radiofrequency amplification, comprises a demodulation of a feedback signal taken from the transmission signal, a comparison between the demodulated feedback signal and the baseband signal, a digital calculation of a predistortion control signal based on the comparison, and an analog predistortion of the analog baseband signal controlled by the predistortion control signal.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

Abstract: An analysis method of a device through a MEMS sensor is provided in which the MEMS sensor includes a control unit and a sensing assembly coupled to the device. The analysis method includes acquiring, through the sensing assembly, first data indicative of an operative state of the device. Testing is performed for the presence of a first abnormal operating condition of the device. If the first abnormal operating condition of the device is confirmed, a self-test of the sensing assembly is performed to generate a quantity indicative of an operative state of the sensing assembly. The self-test includes acquiring, through the sensing assembly, second data indicative of the operative state of the sensing assembly, generating a signature according to the second data, and processing the signature through deep learning techniques to generate said quantity.

Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.

Abstract: The present disclosure is directed to a MOSFET device including a semiconductor body with: a plurality of source regions of a first conductivity type; a plurality of body regions of a second conductivity type, which form a plurality of channel regions; and a drain region of the first conductivity type. The MOSFET device further includes a plurality of insulated gate regions, each of which includes a respective gate conductive region and a respective gate dielectric region, which is partially interposed between the gate conductive region and corresponding source regions and is also partially interposed between the gate conductive region and corresponding channel regions. The MOSFET device further includes a plurality of barrier structures, each of which extends on a corresponding insulated gate region and includes at least one respective first barrier region of silicon nitride.

Abstract: An electronic device includes at least two electronic components. A reset circuit includes: a parity control circuit; at least two first flip-flops, wherein each first flip-flop has an output coupled to at least one of the at least two electronic components; and at least two second flip-flops, wherein each second flip-flop has at least one output coupled to an input of the parity control circuit.

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

Abstract: A MOSFET device of a vertical conduction type has a substrate of silicon carbide having a first conductivity type and a main face. A body region of a second conductivity type extends into the substrate from the main face and has a first depth along a first direction. A first and a second source region of the first conductivity type extend inside the body region starting from the main face parallel to each other and have a second depth along the first direction smaller than the first depth and are mutually spaced by a distance in a second direction perpendicular to the first direction. A body contact region of the second conductivity type extends inside the body region between the first and the second source regions and has a third depth along the first direction greater than or equal to the second depth.

Abstract: A sensor unit is coupled to a machine and configured to detect anomalous behavior of the machine. The sensor unit includes a low power microcontroller that learns to recognize a plurality of operations of the machine. The sensor unit generates mean vector and inverse of a Cholesky decomposition matrix for each operation. During a detection mode the sensor unit computes a Mahalanobis distance for each feature vector, mean vector and first matrix. The sensor unit detects anomalous behavior or classifies the operation of the machine based on the Mahalanobis distances.

Abstract: A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.

Abstract: An authentication method is used in pairing a peripheral device to a companion device. The peripheral device sends a first identifier and a first value of a first counter to the companion device. The companion device verifies whether a pairing table stored in the companion device contains the first identifier. When the pairing table does not include the first identifier the companion device initiates a pairing session. When the pairing table includes the first identifier, the companion device compares the first value to a second value associated with the first identifier in the pairing table. In response to the first value being greater than the second value, the companion devices initiates a nominal session and in response to the first value being lower than or equal to the second value, execution of the method is stopped.

Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

Abstract: A driver circuit includes an input node to receive an input signal for conversion at the output node of a converter, a driver node to provide to a switching power circuit stage in the converter a pulse-width modulated drive signal having an active time, first and second active time generation paths, and a selector circuit coupled to the first and second active time generation paths. The circuit is operable selectively in a first and a second operational mode wherein the driver node receives the pulse-width modulated drive signal having a first active time value generated in the first active time generation path, or a second active time value generated in the second active time generation path. The second active time generation path includes an active time generator network to provide a second active time value with the second active time value adaptively variable to match the first active time value.

Abstract: A control method of an apparatus is provided. The apparatus includes a control unit coupled to a proximity sensor to detect a first distance of a user in a field of view, and coupled to a charge variation sensor to detect an electric/electrostatic charge variation caused by the user in a detection region. The control method includes acquiring a charge variation signal and generating charge variation parameters as a function of the charge variation signal. The control method further includes determining whether a condition on charge variation parameters is verified, and if the condition on charge variation parameters is verified, activating the proximity sensor and acquiring a proximity signal. Proximity parameters are generated as a function of the proximity signal. If a condition on proximity parameters is verified, one or more functionalities of the apparatus are activated.

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.