Patents Assigned to STMicroelectronics (Research & Development) Ltd.
  • Patent number: 12050102
    Abstract: A button device includes a MEMS sensor having a MEMS strain detection structure and a deformable substrate configured to undergo deformation under the action of an external force. The MEMS strain detection structure includes a mobile element carried by the deformable substrate via at least a first and a second anchorage, the latter fixed with respect to the deformable substrate and configured to displace and generate a deformation force on the mobile element in the presence of the external force; and stator elements capacitively coupled to the mobile element. The deformation of the mobile element causes a capacitance variation between the mobile element and the stator elements. Furthermore, the MEMS sensor is configured to generate detection signals correlated to the capacitance variation.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Gattere, Carlo Valzasina, Enri Duqi
  • Patent number: 12050738
    Abstract: A pointing electronic device is provided with: an inertial measurement module, to generate motion input data, indicative of motion of the pointing electronic device, at an input data rate; a pointing determination unit, to implement a pointing algorithm at a processing data rate based on the motion input data, to generate screen-frame displacement data corresponding to 3D-space movements of the pointing electronic device, the processing data rate being higher than the input data rate. The pointing electronic device is further provided with a rate upscaling unit, interposed between the inertial measurement module and the pointing determination unit, to implement a data-rate upscaling of the motion input data, to generate upscaled motion input data to be processed by the pointing determination unit at a data rate matching the processing data rate, via a predictive data reconstruction of missing samples based on the actual motion input data.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: July 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Rizzardini, Lorenzo Bracco, Stefano Paolo Rivolta, Marco Bianco, Paolo Rosingana, Alessandra Maria Rizzo Piazza Roncoroni
  • Publication number: 20240248864
    Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 25, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Loic PALLARDY, Alexandre TORGUE
  • Publication number: 20240250058
    Abstract: A semiconductor die is arranged at a die mounting location of a substrate. The substrate includes an array of electrically conductive leads at the periphery of the substrate. Electrical coupling is provided between the semiconductor die and selected ones of the electrically conductive leads in the array of electrically conductive leads via electrically conductive ribbons. Each ribbon has a body portion with a first width as well as first and second end portions bonded to the semiconductor die and to the electrically conductive leads, respectively. At least one of the first and second end portions of the electrically conductive ribbon includes a tapered portion having a second width smaller than the first width of the body portion.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 25, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Mauro MAZZOLA, Fabio MARCHISI
  • Publication number: 20240249955
    Abstract: An multi-die semiconductor device disclosed herein includes a metallic leadframe with a central die pad encircled by electrically-conductive leads. Mounted on the die pad are two semiconductor dice, each with dedicated bonding pads on the surfaces facing away from the die pad. A layer of laser-activatable material is precisely molded over the dice and the leadframe. This layer forms a network of laser-activated lines: the first subset establishes electrical connections between the dice bonding pads and the leadframe leads, while the second subset interconnects the bonding pads of the first die to those of the second. There are two distinct metallic layers; the lower one, directly on the laser-activated lines, is formed of electroless-plated material, and the upper one, enhancing the structure, is formed of electroplated material, thus providing robust and reliable interconnections within the device.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Paolo CREMA
  • Patent number: 12046324
    Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: July 23, 2024
    Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SAS
    Inventors: Harsh Rawat, Praveen Kumar Verma, Promod Kumar, Christophe Lecocq
  • Patent number: 12048257
    Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Philippe Reynard, Sylvie Del Medico, Philippe Brun
  • Patent number: 12045175
    Abstract: A system includes a processing unit, a memory configured to store at least one first group of instructions and one second group of instructions for execution by the processing unit, the processing unit being configured to sequentially extract from the memory instructions of the first group and instructions of the second group for their execution. The system also includes a controller including a first auxiliary memory configured to store a protection criterion, a comparator configured to compare the storage address of each extracted instruction with the protection criterion, and a control circuit configured to, in response to the storage address meeting the protection criterion, trigger a protection mechanism including at least one prohibition for the processing unit to execute again at least one portion of the instructions of the first group, during the execution of the instructions of the second group.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics (Grand Ouest) SAS
    Inventor: Frederic Ruelle
  • Patent number: 12045378
    Abstract: The present disclosure relates to a method for performing a cryptographic operation, the method including generating a first count value by a monotonic counter of a processing device, transmitting the first count value from the monotonic counter to a memory of the processing device, selecting a first encryption key from the memory based on the first count value, and providing the selected first encryption key to a cryptographic processor.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 23, 2024
    Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Alps) SAS
    Inventors: Franck Albesa, Nicolas Anquet
  • Patent number: 12046987
    Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Laura Capecchi, Riccardo Zurla, Marcella Carissimi
  • Patent number: 12045336
    Abstract: An embedded electronic system includes a volatile memory and a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems. Each high-level operating system executes one or more of applications. The volatile memory includes a first portion reserved for execution data of a first application and a second portion intended to store execution data of a second application. The system is configured so that once the execution data of the first application are loaded in the first portion, the low-level operating system forbids unloading of the execution data of the first application from the first portion so that the execution data of the first application remain in the volatile memory in case of a deactivation or of a setting to standby of the first application.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: July 23, 2024
    Assignees: STMicroelectronics S.r.l., Proton World International N.V.
    Inventors: Olivier Van Nieuwenhuyze, Amedeo Veneroso
  • Patent number: 12048099
    Abstract: A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two face. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Pierino Calascibetta
  • Patent number: 12043540
    Abstract: This disclosure pertains to a microelectromechanical systems (MEMS) device with a tiltable structure, a fixed supporting structure, and an actuation structure with driving arms connected to the tiltable structure by elastic decoupling elements. Described herein, particularly, is a planar stop structure between the driving arms and the tiltable structure, which functions to limit movement in the tiltable plane. This stop structure includes a first projection/abutment surface pair formed by a projection extending from a driving arm and an abutment surface formed by a recess in the tiltable structure. The projection and abutment surface are adjacent and spaced apart in the device's rest condition.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: July 23, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicolo' Boni, Roberto Carminati, Massimiliano Merli
  • Patent number: 12045377
    Abstract: The present disclosure relates to a method for decrypting encrypted data. The method includes generating a first count value by a monotonic counter of a processing device, deriving, using a key derivation circuit, a first encryption key based on the first count value, transmitting the first encryption key to a cryptographic processor; and decrypting, based on the first encryption key, first encrypted data.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: July 23, 2024
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SAS
    Inventors: Franck Albesa, Nicolas Anquet
  • Publication number: 20240243698
    Abstract: An envelope detector receives a modulated signal and a differential stage coupled to the detector produces a replica modulated signal compared to produce a PWM-modulated signal having on and off times. A first switch is actuated to short-circuit the input to the envelope detector. A second switch is actuated to feed back to a storage capacitor a signal indicative of the difference between inputs to the differential stage. A third switch is actuated to short-circuit an input to the comparator. Logic circuitry activates the switched to implement offset compensation where: the first, second and third switches are actuated in the absence of the PWM-modulated signal during start-up and standby phases; and the first, second and third switches are actuated during off times of the PWM-modulated signal in a working phase alternating with the start-up/standby phases.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 18, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Nunzio SPINA, Alessandro CASTORINA, Giuseppe PALMISANO
  • Publication number: 20240242749
    Abstract: A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 18, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Riccardo CONDORELLI, Antonino MONDELLO, Michele Alessandro CARRANO, Michele BOTTARO, Salvatore COSTA, Jacques TALAYSSAT
  • Publication number: 20240243712
    Abstract: A differential pair circuit includes a first branch and a second branch having a common first node. Each of the first and second branches includes at least one transistor having a conduction node directly connected to the common first node. A third branch couples the common first node to a power supply node. The third branch includes a current source in series with a resistive element.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 18, 2024
    Applicant: STMicroelectronics (Alps) SAS
    Inventors: Vratislav MICHAL, Samuel FOULON
  • Patent number: 12040724
    Abstract: A bridge rectifier and associated control circuitry collectively form a “regtifier” which rectifies an input time varying voltage and regulates the rectified output voltage produced without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). The transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. This modulation is based upon both a voltage feedback signal and a current feedback signal.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Yannick Guedon
  • Patent number: 12040263
    Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto Tiziani
  • Patent number: 12040722
    Abstract: In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Claudio Adragna