Abstract: A method performs a correction of an ionospheric error affecting pseudo-ranges measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of a constellation of satellites. The method is part of a navigation processing procedure performed at the GNSS receiver. The method utilizes pseudo range measurements previously calculated by the GNSS receiver, obtained from a plurality of carrier signals in the satellite signals. The method includes performing a correction procedure of the pseudo-range measurements, by calculating ionospheric error correction values for the pseudo-range measurements.

Abstract: A circuit is configured to perform an operation between a volatile memory and a cryptographic circuit in response to a write access request for writing one or more data values in the memory. The access request further includes a storage address in the memory. The operation includes steps for: writing the one or more data values; and for each of the one or more data values, generating a write access request, in the cryptographic circuit, for the data value, and generating a write access request, in the cryptographic circuit of the storage address. Additionally, a verification, in response to a read access request, from the processor, of a verification value is performed. The verification operation includes steps for: comparing the verification value with a reference value; and based on the comparing, authorizing access the volatile memory only for reading.

Abstract: Laser direct structure (LDS) material is molded onto a semiconductor chip arranged on a substrate. The LDS material has a first thickness between a front surface of the LDS material and the substrate. A portion of the LDS material is removed (with a blade, for instance) to form a cavity having an end wall between the front surface of the LDS material and an electrically conductive formation on the substrate. At the cavity, the LDS material has a second thick ness smaller than the first thickness. Laser beam energy is applied to the LDS material at the end wall of the cavity to structure therein one or more vias that extend between the end wall of the cavity and the electrically conductive formation. The semiconductor chip and the electrically conductive formation are electrically coupled with electrically conductive material grown in the one or more vias laser structured in the LDS material.

Abstract: A method is for synchronizing power consumption data with trace data in a microcontroller debugging system. The method involves periodically sending synchronization requests from a host device to a synchronization manager within a debug probe. The synchronization manager retrieves the current power acquisition cycle number from a power acquisition circuit in response to each request, corresponding to a current sample of microcontroller power consumption. Each synchronization request, along with the retrieved cycle number, is sent to a protocol manager, which transmits the request to a microcontroller's debug-port. Upon receiving acknowledgment from the microcontroller, the protocol manager communicates these to the synchronization manager. The synchronization manager measures the latency between sending each synchronization request and receiving its acknowledgment, which is indicative of synchronization quality.

Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.

Abstract: A device includes charge pumps, wherein each charge pump has an input receiving an input voltage, another input receiving a periodic control signal and an output delivering an output voltage. Each charge pump is selectively enabled or disabled. A first circuit delivers an error signal based on a difference between the output voltage and a reference voltage. A second circuit changes an operating parameter of the charge pumps on the basis of the error signal. A third circuit compares a current value of the operating parameter with two thresholds and, based on the result of the threshold comparisons, controls one of an increase in, a decrease in, and a retention of a number of enabled charge pumps.

Abstract: Microelectromechanical device comprising a supporting body, containing semiconductor material and a movable mass, constrained to the supporting body with a relative degree of freedom with respect to at least one motion direction, within a range of admissible positions. The device also comprises stopper elements, operable by the movable mass due to movements along the at least one motion direction and configured to apply stop forces to opposite sides of the movable mass, transversely to the at least one motion direction, when the movable mass reaches a respective endpoint of the range of admissible positions, so as to prevent the movable mass from exceeding the respective endpoint.

Abstract: A converter circuit is configured to convert a DC voltage into an AC voltage using a first thyristor and second thyristor in series in a first branch, a third thyristor and fourth thyristor in series in a second branch in an antiparallel configuration to the first branch, and a first transistor and second transistor in series in a third branch. When the AC voltage is equal to zero, and when the first thyristor is conductive and the first and second transistors are non-conductive, a first positive current is applied to the gate of the antiparallel third thyristor to control turn on and ensure that the current circulating in the first thyristor falls below the holding current.

Abstract: Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.

Abstract: Semiconductor chips are arranged on a first surface of a common electrically conductive substrate having an opposite second surface. The substrate includes adjacent substrate portions having mutually facing sides with sacrificial connecting bars extending between adjacent mutually facing sides. A solderable metallic layer is present on the second surface extending over the sacrificial connecting bars. The solderable metallic layer is selectively removed (by laser ablation or etching, for example) from at least part of the length the sacrificial connecting bars. The common electrically conductive substrate is then cut along the length of the elongate sacrificial connecting bars to provide singulated individual semiconductor devices. Undesired formation of electrically conductive filaments or flakes bridging parts of the substrate intended to be mutually isolated is countered.

Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.

Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

Abstract: The present disclosure is directed to a device and method for accurately estimating a write self-time of a memory array. The write self-time is estimated by performing a simulated write operation on a write self-time bit cell having the same structure and arrangement as each of the bit cells of the memory array. The write operations on the bit cells of the memory array are stopped in response to detecting completion of the simulated write operation.

Abstract: A semiconductor die is arranged at a first surface of a die pad. The die pad has a peripheral edge and a second surface opposite to the first surface that includes a first region and a second region surrounding the first region. The second region extends to the peripheral edge of the die pad from a border line at the first region and includes a recessed formation extending continuously along the border line. An insulating encapsulation is molded onto the die pad with the first region of the second surface left uncovered and the second region of the second surface of the die pad being covered by the insulating encapsulation that fills the recessed formation. The recessed formation has a variable recess depth between the border line and the peripheral edge of the die pad to provide an extended length delamination path from the border line to the semiconductor die.

Abstract: The HEMT device has a body including a heterostructure configured to generate a 2-dimensional charge-carrier gas; and a gate structure which extends on a top surface of the body and is biasable to electrically control the 2-dimensional charge-carrier gas. The gate structure has a channel modulating region of semiconductor material; a functional region of semiconductor material; and a gate contact region of conductive material. The functional region and the gate contact region extend on a top surface of the channel modulating region and the gate contact region is arranged laterally with respect to the functional region. The channel modulating region has a different conductivity type with respect to the functional region.

Abstract: The present disclosure is directed to human presence detection with an infrared sensor. The human presence detection utilizes signal regularization and edge detection to minimize the effect of drift on the human presence detection. The human presence detection is accurate regardless of changes in ambient temperatures.

Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.

Abstract: The present disclosure relates to a regulator including a first transistor coupling an application node of a first power supply voltage to an output node of the regulator supplying a first regulated voltage; a feedback loop supplying a control signal to the first transistor and comprising a first charge pump circuit; a control signal generator of the first charge pump circuit; and a drop-down circuit between the control signal generator and the charge pump circuit.

Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.

Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.