Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.
Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
Abstract: In embodiments, a method is provided that includes writing a static data image in an invariant part of a non-volatile memory of an integrated circuit used to store an operating system; writing a set of personalization data in the static data image representing data specific to the integrated circuit; storing a subset of the set of personalization data in a reserved area of the non-volatile memory by reserving the reserved area and storing commands for writing the set of personalization data by an application or the operating system; converting the commands with a known code to obtain an inner command script, the inner script including the commands as encoded; storing the inner command script in the reserved area of the non-volatile memory; decoding and executing the inner command script to obtain the commands during an activation of the integrated circuit; and executing the commands by the integrated circuit.
Abstract: The present disclosure relates to an USB PD-type interface including a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node, and a fifth node; a MOS transistor connected between the fifth node and the second node; a bipolar transistor having a collector connected to a gate of the MOS transistor and an emitter connected to the fourth node or to the fifth node; and a circuit configured to deliver a control potential to a base of the bipolar transistor determined from a current in the first resistor.
Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
Abstract: An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.
Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.
Abstract: A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. An amplifier stage coupled to the intermediate node produces an amplified rectified signal at an output node that is indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage includes a resistive element coupled between the intermediate node and the supply voltage node in parallel to the load circuit.
Type:
Grant
Filed:
March 25, 2022
Date of Patent:
September 17, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Nunzio Spina, Egidio Ragonese, Giuseppe Palmisano
Abstract: A thin-film lithium ion battery includes a negative electrode layer, a positive electrode layer, an electrolyte layer disposed between the positive and negative electrode layers, and a lithium layer with lithium pillars extending therefrom formed in the negative electrode layer adjoining the electrolyte layer.
Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.
Abstract: In one embodiment, a method for detecting functional state of a microelectromechanical (MEMS) sensor is described. The method includes monitoring an input common-mode feedback (ICMFB) voltage generated by an ICMFB circuit coupled to the MEMS sensor through a plurality of nodes. The method also includes determining, using the monitored ICMFB voltage, whether all of the plurality of nodes of the MEMS sensor are electrically connected to the ICMFB circuit.
Abstract: A blocking element is provided for connecting an electronic, micro-mechanical and/or micro-electro-mechanical component, in particular for controlling the propulsion of an electric vehicle. The pin blocking element is formed by a holed body having a first end, a second end and an axial cavity configured for fittingly accommodating a connecting pin. A first flange projects transversely from the holed body at the first end and a second flange projects transversely from the holed body at the second end. The first flange has a greater area than the second flange and is configured to be ultrasonically soldered to a conductive bearing plate to form a power module.
Type:
Grant
Filed:
September 30, 2021
Date of Patent:
September 17, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Agatino Minotti, Francesco Salamone, Massimiliano Fiorito, Alessio Scordia, Manuel Ponturo
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.
Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.
Abstract: The image sensor includes an array of photosensitive pixels comprising at least two sets of at least one pixel, control circuit configured to generate at least two different timing signals and adapted to control an acquisition of an incident optical signal by the pixels of the array, and distribution circuit configured to respectively distribute the at least two different timing signals in the at least two sets of at least one sensor, during the same acquisition of the incident optical signal.
Abstract: An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die.
Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.
Abstract: The present disclosure relates to a pulse width modulation circuit of a switched-mode power supply formed in and on a monolithic semiconductor substrate with a face coated with a gallium nitride layer, said circuit being adapted to control a power transistor of said switched-mode power supply.
Abstract: A HEMT transistor is formed on a semiconductor body having a semiconductive heterostructure. A gate region of a semiconductor material, is arranged on the semiconductor body and has lateral sides. Sealing regions of non-conductive material extend on the lateral sides of the gate region; and a passivation layer of non-conductive material has surface portions extending on the semiconductor body, on both sides of the gate region and at a distance therefrom. The sealing regions and the passivation regions have different characteristic, such as are of different material or have different thicknesses.
Type:
Application
Filed:
March 1, 2024
Publication date:
September 12, 2024
Applicant:
STMicroelectronics International N.V.
Inventors:
Cristina TRINGALI, Aurore CONSTANT, Maria Eloisa CASTAGNA, Ferdinando IUCOLANO