Patents Assigned to STMicroelectronics (Research& Development)
-
Publication number: 20240304713Abstract: An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.Type: ApplicationFiled: February 29, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Ferdinando IUCOLANO, Aurore CONSTANT, Cristina TRINGALI, Maria Eloisa CASTAGNA
-
Publication number: 20240306401Abstract: The present disclosure relates to a process that includes the simultaneous formation of a first transistor in and on a first region of a substrate, of a second transistor in and on a second region of the substrate, of a third transistor in and on a third region of the substrate and of a memory cell in and on a fourth region of the substrate. The method includes the following successive steps: forming a first gate stack on the first region, a second gate stack on the second region, a third gate stack on the third region and a fourth stack on line with the fourth region; simultaneously etching a part of the third gate stack and the fourth stack the first and the second gate stacks being protected with a first mask; and simultaneously etching the first and the second gate stacks, the third gate stack and the fourth region of the semiconductor substrate being protected with a second mask.Type: ApplicationFiled: February 26, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Remy BERTHELON, Olivier WEBER
-
Publication number: 20240305145Abstract: A wireless power receiving appliance is configured to wirelessly receive power from a wireless power transmitter. The appliance includes: an NFC device electromagnetically coupled to another NFC device of the wireless power transmitter and a field strength indicator. The field strength indicator: receives from an NFC antenna of the NFC device a representative signal of the strength of the NFC field between the NFC device and the another NFC device, compares a value of the representative signal with at least one reference value, and emits a user signal depending on the comparison between the value of the representative signal and the at least one reference value. The user signal displays an indication of the position of the appliance with respect to the wireless power transmitter.Type: ApplicationFiled: March 6, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Martin RAMPETSREITER, Rene WUTTE, Asmira HUSKIC, Martin DENDA
-
Publication number: 20240304731Abstract: An electronic device includes first and second diffused resistors in contact with each other to form a PN junction. The device is configured so that a potential difference between the first and second resistors is constant at any point of the PN junction. The PN junction is reverse-biased.Type: ApplicationFiled: March 4, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Francois TAILLIET, Marc BATTISTA
-
Publication number: 20240302219Abstract: Disclosed herein are thermal sensor devices including TMOS devices with a mass suspended over a cavity by springs extending between a frame and the mass. The thermal sensor devices include stoppers that limit upward and/or downward movement of the springs and therefore the mass. These stoppers are formed from sidewalls supporting a top cap over the frame, springs, and mass. The stoppers are constructed by using various overlapping metal layers during fabrication. Details of forming the stoppers using these overlapping metal layers are contained here.Type: ApplicationFiled: March 10, 2023Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Federico VERCESI, Silvia NICOLI, Cinzia DE MARCO
-
Publication number: 20240303092Abstract: An asynchronous finite state machine has states coupled by transitions each implemented by a flip-flop. Each flip-flop supplies a bit of a state of arrival of the corresponding transition, and receives a bit of an initial state of this transition on its data input and a first signal dedicated to the flip-flop on its control input. A circuit supplies, for each transition, a second signal of request for the transition. Another circuit generates based on the second signals, at each request for a transition and in the absence of a pulse of the first signals, a pulse of the first signal dedicated to the flip-flop of this transition, and a pulse of the first signal dedicated to each flip-flop supplying a bit to the flip-flop of the transition.Type: ApplicationFiled: March 6, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventor: David CHESNEAU
-
Publication number: 20240304710Abstract: A HEMT transistor has a body having a top surface and a heterostructure, and a gate region having a semiconductor material and arranged on the top surface of the body. The gate region has a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall. The HEMT device further has a sealing layer of non-conductive material that extends on and in contact with the first and the second lateral sidewalls of the gate region; and a passivation layer of non-conductive material that has a surface portion. The surface portion extends on the top surface of the body, laterally to the first lateral sidewall of the gate region. The sealing layer and the passivation layer have different geometrical parameters and/or are of different material.Type: ApplicationFiled: February 29, 2024Publication date: September 12, 2024Applicant: STMicroelectronics International N.V.Inventors: Cristina TRINGALI, Aurore CONSTANT, Maria Eloisa CASTAGNA, Ferdinando IUCOLANO
-
Patent number: 12088326Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.Type: GrantFiled: September 8, 2022Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Abhishek Jain
-
Patent number: 12088085Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.Type: GrantFiled: January 20, 2023Date of Patent: September 10, 2024Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics International N.V.Inventors: Manoj Kumar, Ravinder Kumar, Nicolas Demange
-
Patent number: 12086094Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.Type: GrantFiled: September 4, 2020Date of Patent: September 10, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Arnaud Dehamel
-
Patent number: 12084341Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.Type: GrantFiled: October 12, 2021Date of Patent: September 10, 2024Assignee: STMicroelectronics S.r.l.Inventors: Nicolo' Boni, Lorenzo Vinciguerra, Roberto Carminati, Massimiliano Merli
-
Patent number: 12086008Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.Type: GrantFiled: September 12, 2022Date of Patent: September 10, 2024Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O.Inventors: Jerome Lacan, Remi Collette, Christophe Eva, Milan Komarek
-
Patent number: 12086568Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.Type: GrantFiled: April 14, 2023Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Rupesh Singh
-
Patent number: 12088310Abstract: A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i?1 in the sequence.Type: GrantFiled: March 29, 2023Date of Patent: September 10, 2024Assignee: STMicroelectronics S.r.l.Inventors: Davide Nicolo Fortunato, Antonino Calcagno, Marco Vinciguerra, Angelo Scuderi, Gaetano Cosentino
-
Patent number: 12088429Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.Type: GrantFiled: February 22, 2022Date of Patent: September 10, 2024Assignees: STMicroelectronics Design and Application S.R.O., STMicroelectronics Application GmbHInventors: Fred Rennig, Vaclav Dvorak
-
Patent number: 12086358Abstract: A touch status monitor method includes detecting a touch on a touch screen when operating in a low-power detect scan mode. The method further includes, in response to detecting the touch, switching from the low-power detect scan mode to a low-power active scan mode and labeling the current event as a touch down event. The method further includes, in response to labeling the current event as the touch down event, applying a lock to prevent updating a baseline when entering the low-power detect scan mode. And the method further includes, in response to detecting that the touch has left the touch screen, releasing the lock, labeling the current event as a touch up event, switching from the low-power active scan mode to the low-power detect scan mode, and updating the baseline.Type: GrantFiled: November 2, 2023Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Qiang Ma, Yuan Yun Wang
-
Patent number: 12085601Abstract: A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated.Type: GrantFiled: January 4, 2022Date of Patent: September 10, 2024Assignee: STMicroelectronics S.r.l.Inventors: Romeo Letor, Veronica Puntorieri
-
Patent number: 12087356Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.Type: GrantFiled: June 27, 2022Date of Patent: September 10, 2024Assignee: STMicroelectronics International N.V.Inventors: Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
-
Patent number: 12087873Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.Type: GrantFiled: March 23, 2022Date of Patent: September 10, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
-
Patent number: 12087708Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.Type: GrantFiled: October 21, 2021Date of Patent: September 10, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment