Abstract: In a solid state image sensor having a pixel array, a first frame is imaged using varying exposure times in a series of zones. The exposure time for a subsequent frame is selected from the results of the first frame, The exposure times are controlled in a rolling blade manner by controlling the number of lines between reset and readout. The sensor is particularly suited to use in bar code readers.

Abstract: An integrated circuit, method of making an integrated circuit and method of addressing peripherals of an integrated circuit are disclosed for preventing copied software from running on unauthorised hardware. A permanent key is embedded in the integrated circuit and used to transform a peripheral access address output by a processor of the integrated circuit. The transformed access address is supplied to a peripheral address decoder f the integrated circuit, which allows the processor to access a corresponding peripheral. A method of supplying integrated circuits to prevent copied software from running on unauthorized hardware is also disclosed.

Abstract: Combination circuitry for combining a plurality of multi-bit partial product terms includes at least one stage arranged to receive a first number of input bits. At least one stage includes at least one combiner having: a first logic device comprising an input arranged to receive a first set of the first number of input bits and an output arranged to output a first combined result; a second logic device comprising a first input arranged to receive a second set of the first number of input bits, a second input connected to receive the first combined result, a first output arranged to output a second combined result, and a second output arranged to output a first combined bit group; and a third logic device comprising an input connected to receive the second combined result and an output arranged to output a second combined bit group, whereby the first combined bit group is available for a further stage of the combination circuitry before the second combined bit group.

Abstract: Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first circuit arranged to receive a first set of the plurality of partial product term bits for the at least one compression column, the first circuit further arranged to combine the first set of term bits to produce a first combined term bit set; and a second circuit arranged to receive a second set of the plurality of term bits for the at least one compression column and all of the first combined term bit set.

Abstract: An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of varying bit length of m bits or less; an addition circuit having m columns each having n inputs, wherein bits of said partial products are applied to said inputs for combining said partial products into a result leaving certain of said inputs unused; and a rounding bit generator connected to supply a rounding bit to at least one of said unused inputs in one of said m columns at a bit position to cause said result to be rounded.

Abstract: An imaging system includes an image sensor, a digital image sensing device and a host system. The digital image sensing device provides image data in a plurality of formats, suitable for the differing requirements of different applications running on a host system.

Abstract: A system for processing a received signal having at least one code applied thereto, said received signal having a frequency, said system comprising: first correlator circuitry arranged to correlate the received signal with a first code to provide an output; second correlator circuitry arranged to correlate the received signal with a second code to provide an output, wherein said first code and said second code are different; and processing means for processing together the outputs of said first and second correlator circuitry to cancel said frequency.

Abstract: An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.

Abstract: A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set. The combining circuit also includes a second circuit, arranged to receive a second set of the plurality of terms and to combine the second set of terms to produce a second combined term set. The combining circuit further includes a third circuit, arranged to receive the first and second combined term sets and to combine the first and second combined term sets to produce a third combined term set. The combining circuit outputs the first combined term set as a first combination result and the third combined term set as a second combination result.

Abstract: A multiplier circuit multiplies a first and a second operand. The circuit includes a sectioning circuit arranged to section the first operand into a first number of parts and a multiplier arranged to receive the second operand and a second number of the first number of parts. The multiplier is further arranged to generate only a second number of product terms, each product term being one of the second number of parts multiplied by the second operand.

Abstract: The image sensor has a plurality of pixels arranged in rows and columns to form a pixel array, each pixel column having a column bitline. The image sensor includes a column readout for each column bitline and at least one additional column readout. The additional column readout may be selectively connected to one of the column bitlines. In one embodiment, a defective column readout can be isolated and the additional column readout used as a replacement.

Abstract: The electronic imaging system includes a sensing device between a reset supply and a pixel array. While the pixels of the array are held in reset, the varying current supplied by the reset supply is monitored to provide information on scene changes.

Abstract: The image sensor includes a plurality of pixels, arranged in rows and columns to form a pixel array, each pixel having a pixel output. The image sensor includes at least two column bitlines for each pixel column, each column bitline connected to each pixel output in the pixel column and to a common readout amplifier. In one embodiment, the bitlines are not in the same plane and multiple bitlines are positioned one above the other, maximizing pixel efficiency.

Abstract: A charge pump includes a transistor of the charge pump modified to regulate a supply voltage to substantially reduce noise from the supply voltage when charging the capacitor of the charge pump and subsequently reduces noise at the voltage output. The charge pump may have a regulating transistor for charging or for pumping or for both. The regulating transistor requires a regulated bulk voltage and a modulated gate voltage to enable regulation of the supply voltage. The regulated bulk voltage may be supplied by a small regulator.