Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.

Abstract: An electronic device applies a frequency offset function to a first signal having a first frequency. The device includes a delay element configured to output a second signal corresponding to the first signal delayed by a duration equal to a first period of said signal divided by four. A circuit branch includes a first circuit configured to divide the frequency of the first signal by a given number coupled in series with a second circuit configured to implement an integration. The circuit branch outputs a third signal and a fourth signal. A single side band mixing circuit processes the first signal, second signal, third signal and fourth signal to generate an output signal.

Abstract: A coupling and chaining bridge is configured to receive an original data value via a first bus coupled to one of a system bus of an electronic device and a first peripheral circuit of the electronic device. The original data value is transmitted by the coupling and chaining bridge to a second bus of the electronic device coupled to the other of the system bus and the first peripheral circuit. The coupling and chaining bridge is further configured to intercept the original data value and transmit a copy of the original data value to a third bus of the device that is coupled to a second peripheral circuit of the device.

Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

Abstract: A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

Abstract: A memory cell comprising a stack of a conductive via, of a layer made of a phase-change material, and of a first electrode, the memory cell being covered with an encapsulation layer made of a silicon nitride having a density or volumic mass smaller than 2.2 g/cm3. A method of manufacturing a memory cell and a system having an integrated memory circuit that includes a plurality of memory cells is also provided.

Abstract: A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

Abstract: Integrated electronic device including: a semiconductor body of silicon delimited by a front surface and including at least a first semiconductive region of a first conductivity type, which extends into the semiconductor body starting from the front surface, and a second semiconductive region of a second conductivity type, which extends below the first semiconductive region; a dielectric capping region; a trench which extends through the dielectric capping region and through a front portion of the semiconductor body, in such a way that a part of the first semiconductive region laterally faces the trench, said trench partly extending inside the second semiconductive region; a conductive contact structure extending into the trench and including: a coating region of titanium silicide, which coats the bottom of the trench, in contact with the second semiconductive region, and also laterally coats the part of the first semiconductive region laterally facing the trench; and an inner conductive region.

Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.

Abstract: The present disclosure is directed to an optical sensor package with light shielding material covering five sides. The optical sensor package includes a transparent layer, a substrate layer, sensor elements between the transparent layer and the substrate layer, a solder mask on the side of the substrate layer opposite the transparent layer, and layer of molding material covering five sides of the optical sensor package. The solder mask and layer of molding material prevent light from entering the sides of the optical sensor package or from traveling through the substrate layer and reflecting toward the sensor elements.

Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.

Abstract: A “package-less” integrated circuit semiconductor device is produced by laminating first and second insulating films on opposed first and second surfaces of a semiconductor wafer having semiconductor dice integrated therein. Electrically conductive formations towards die pads of the semiconductor dice are provided in vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer. The semiconductor wafer provided with these electrically conductive formations is singulated at separation lines between neighboring semiconductor dice to produce individual semiconductor devices. Each device has: opposed first and second device surfaces having protective portions of the first and second insulating films laminated thereon, and side surfaces extending between the opposed first and second device surfaces, these side surfaces being left uncovered by the first and second insulating films.

Abstract: A method for manufacturing a MEMS device includes forming a first solid body by forming, on a substrate, a layered structure having a thickness of a value comprised between 4 and 10 ?m, with the layered structure having a first surface that is uniformly flat or planar throughout the extension thereof that faces the substrate. The method further includes forming, on a second surface of the layered structure opposite to the first surface in a direction, multiple transducer devices. The method then proceeds with coupling the first solid body to a supporting structure, and completely removing the substrate to expose said uniformly flat or planar surface.

Abstract: An electronic device includes a memory and includes a plurality of word lines selectively driven by a decoder, with each pair of adjacent word lines having an underdrive circuit coupled therebetween. That underdrive circuit includes first and second transistors source/drain coupled in series with one another between the pair of adjacent word lines, the first and second transistors being replicas of a pull-down transistor and a pass gate transistor of bitcells the memory. One of the first and second transistors has its gate driven by a supply voltage and the other of the first and second transistor has its gate driven by a first read assist control signal.

Abstract: The present disclosure is directed to an optical sensor package with light shielding material covering five sides. The optical sensor package includes a transparent layer, a substrate layer, sensor elements between the transparent layer and the substrate layer, a first layer of light shielding material on the side of the substrate layer opposite the transparent layer, and a second layer of light shielding material covering five sides of the optical sensor package. The first and second layers of light shielding material prevent light from entering the sides of the optical sensor package or from traveling through the substrate layer and reflecting toward the sensor elements.

Abstract: An integrated circuit optical package includes a support substrate having a mounting face and an electrical interconnection network between the mounting face and contact pads located on a lower face of the support substrate. A cap includes a lateral wall fastened on the mounting face and an upper wall including a first opening. A first optical element is fastened on the upper wall of the cap to seal the first opening. An electromagnetic shielding element is embedded in the cap and configured to be coupled to a reference supply point via the interconnection network and at least one contact pad. A first electronic chip is mounted on the mounting face and in optical cooperation with the first optical element.

Abstract: The present disclosure is directed to a device and method for human fall detection solution. Fall detection is performed by a low power inertial measurement unit (IMU) that is communicatively coupled between a pressure sensor and an application processor. The IMU includes one or more motions sensors, such as an accelerometer and gyroscope. The application processor is the main processor of the containing device. The IMU receives pressure sensor data from the pressure sensor, and executes the fall detection using both the pressure sensor data and accelerometer data.

Abstract: A power module includes an insulating body having a first main face and a second main face; a first contact plate and a second contact plate, respectively protruding through the first main face and through the second main face of the insulating body and accessible from the outside; a first power plate and a second power plate, at least partially embedded in the insulating body and facing each other. Power devices of a first group are accommodated on the first power plate and coupled to the first contact plate. Power devices of a second group are accommodated on the second power plate and coupled to the second contact plate. The first contact plate, the second contact plate, the first power plate and the second power plate, are stacked in a direction perpendicular to the first power plate and the second power plate.

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

Abstract: A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.