Patents Assigned to STMicroelectronics (Rousset) SAS
  • Method for managing requests for access to random access memory and corresponding system
    Patent number: 11495275
    Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christophe Eva, Jean-Michel Gril-Maffre
  • Method for detecting moisture in an integrated circuit, and associated integrated circuit
    Patent number: 11493470
    Abstract: Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 8, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Matthias Vidal-Dho, Quentin Hubert, Pascal Fornara
  • MICROELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE
    Publication number: 20220352147
    Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Romeric GAY, Abderrezak MARZAKI
  • Non volatile static random access memory device and corresponding control method
    Patent number: 11488666
    Abstract: An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: November 1, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • INTEGRATED CIRCUIT INCLUDING AT LEAST ONE CAPACITIVE ELEMENT AND CORRESPONDING MANUFACTURING METHOD
    Publication number: 20220344327
    Abstract: A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 27, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • PHASE-CHANGE MEMORY
    Publication number: 20220336736
    Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe BOIVIN, Daniel BENOIT, Remy BERTHELON
  • METHOD FOR IMPLEMENTING AN NFC TRANSACTION
    Publication number: 20220311476
    Abstract: The present disclosure relates to a method implemented by a first NFC device, wherein the establishment of a transaction with a second NFC device configured in reader mode is performed when the signal level received by the first device, configured in card mode, reaches a first threshold, depending on the type of modulation technology of the second device.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 29, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nicolas CORDIER
  • ERROR DETECTION
    Publication number: 20220310192
    Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice ROMAIN, Mathieu LISART
  • Starting of a switched-mode power supply
    Patent number: 11456661
    Abstract: The process for starting a power supply circuit which includes a switched-mode power supply is performed using: a first phase during which, if an output voltage of the switched-mode power supply is lower than a first voltage, the switched-mode power supply operates in pulse width modulation mode to increase its output voltage up to said first voltage; and when the output voltage has reached the first voltage, a second phase during which the switched-mode power supply operates in a bypass mode.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 27, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien Ortet, Cedric Thomas
  • Protection of an iterative calculation
    Patent number: 11456853
    Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 27, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Ibrahima Diop, Yanis Linge
  • Temperature detection device and method using sets of DC voltages
    Patent number: 11454554
    Abstract: Two sets of the DC voltages are determined from among sets of DC voltages. At a first temperature, a first voltage of one of the two sets and a first voltage of the other one of the two sets surround a detection voltage that varies substantially proportionally to temperature. The detection voltage is compared with a second voltage of one of the two sets.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 27, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Bruno Gailhard
  • CONFIGURATION OF A TRANSACTION IN A CONTACTLESS ELECTRONIC DEVICE
    Publication number: 20220300781
    Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with different communication protocols or the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes stopping, by the contactless communication circuit, the transmission of answers of the contactless communication device to requests transmitted by a proximity coupling reader during a transaction initiated by the reader to cause the initiation by the reader of a new transaction.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Olivier VAN NIEUWENHUYZE, Jean-Marc GRIMAUD
  • RANDOM NUMBER GENERATOR
    Publication number: 20220283896
    Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 8, 2022
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Albert MARTINEZ, Patrick HADDAD
  • Device for protecting encrypted data and associated method
    Patent number: 11436346
    Abstract: A method and device for protecting encrypted data are disclosed. In an embodiment an integrated circuit includes a secure module including a first register containing a first mask and a second register containing masked data, the first mask and the masked data forming a secret key and a processor configured to generate a second mask and mask the secret key with the second mask when the secret key is not used for an encryption operation and during reception of a validation signal, wherein the first and second registers are disposed in the secure module so that the outputs of the registers are not simultaneously optically viewable.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: September 6, 2022
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabien Journet, Yanis Linge
  • Protection of the execution of cipher algorithms
    Patent number: 11431491
    Abstract: Systems and methods for protecting secret or secure information involved in generation of ciphered data by circuitry. The circuitry includes data paths and key paths that operate to perform cipher operations to generate a plurality of key shares and a plurality of data shares using a key and data as input. The data and the key may be masked by at least one mask. The plurality of key shares may be generated using the key and a first mask. The plurality of data shares are generated using key shares, the data, and a second mask.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 30, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Thomas Sarno, Yanis Linge
  • NFC CHARGING
    Publication number: 20220271568
    Abstract: A device includes: an NFC controller; a microcontroller; a charging circuit for an external battery; an energy recovery device; an antenna; and a switch. The NFC controller is configured to selectively control the switch in order to couple the energy recovery device to the charging circuit.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 25, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas CORDIER, Anthony TORNAMBE, Jeremy QUIGNON
  • Fabrication process comprising an operation of defining an effective channel length for MOSFET transistors
    Patent number: 11424342
    Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 23, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Franck Julien
  • Phase-change memory with insulated walls
    Patent number: 11411177
    Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 9, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
  • PROCESSOR AUTHENTICATION METHOD
    Publication number: 20220244961
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 4, 2022
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Michael PEETERS, Fabrice MARINET
  • Device of physically unclonable function with transistors, and manufacturing method
    Patent number: 11405223
    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier