Patents Assigned to STMicroelectronics (Rousset) SAS
  • Method for writing in a non-volatile memory according to the ageing of the memory cells and corresponding integrated circuit
    Patent number: 11615857
    Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 28, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Enrico Castaldo, Francesca Grande, Santi Nunzio Antonino Pagano, Giuseppe Nastasi, Franco Italiano
  • INTEGRATED CIRCUIT INCLUDING STANDARD CELLS AND AT LEAST ONE CAPACITIVE FILLING STRUCTURE
    Publication number: 20230088967
    Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 23, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Jean-Marc VOISIN
  • Device and method for allocating intermediate data from an artificial neural network
    Patent number: 11609851
    Abstract: According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 21, 2023
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Laurent Folliot, Emanuele Plebani, Mirko Falchetto
  • ELECTRONIC SYSTEM COMPRISING A CONTROL UNIT CONFIGURED TO COMMUNICATE WITH A MEMORY
    Publication number: 20230085493
    Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 16, 2023
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application S.R.O.
    Inventors: Jerome LACAN, Remi COLLETTE, Christophe EVA, Milan KOMAREK
  • Method of manufacturing an integrated circuit comprising a capacitive element
    Patent number: 11605702
    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: March 14, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Device and method for touch sensing
    Patent number: 11604082
    Abstract: An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: March 14, 2023
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Laurent Beyly, Olivier Richard, Kenichi Oku
  • PROTECTION OF A CRYPTOGRAPHIC OPERATION
    Publication number: 20230074513
    Abstract: The present disclosure relates to a cryptographic method comprising: multiplying a point belonging to a mathematical set with a group structure by a scalar by performing: the division of a scalar into a plurality of groups formed of a same number w of digits, w being greater than or equal to 2; and the execution, by a cryptographic circuit and for each group of digits, of a sequence of operations on point, the sequence of operations being identical for each group of digits, at least one of the operations executed for each of the groups of digits being a dummy operation.
    Type: Application
    Filed: August 18, 2022
    Publication date: March 9, 2023
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Guilhem ASSAEL
  • METHOD, SYSTEM, AND DEVICE FOR SOFTWARE AND HARDWARE COMPONENT CONFIGURATION AND CONTENT GENERATION
    Publication number: 20230075227
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 9, 2023
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics (Grand Ouest) SAS
    Inventors: Emmanuel GRANDIN, Nabil SAFI, Maxime DORTEL, Laurent MEUNIER, Frederic RUELLE
  • Method and device for detecting the possible presence of at least one digital pattern within a signal
    Patent number: 11601310
    Abstract: In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: March 7, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yoann Bouvet
  • POWER SWITCH
    Publication number: 20230064471
    Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.
    Type: Application
    Filed: August 10, 2022
    Publication date: March 2, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Laurent LOPEZ
  • Method for managing an operation for modifying the stored content of a memory device, and corresponding memory device
    Patent number: 11593284
    Abstract: An embodiment method for managing an operation for modifying the content of the memory plane of a memory device coupled to a processing unit, comprises a communication by the processing unit to the memory device of a control of the operation, an execution of the operation by the memory device, and at the end of the operation, a communication by the memory device itself to the processing unit of information indicating the end of the operation.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 28, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Gilles Dionis
  • Direct memory access
    Patent number: 11593289
    Abstract: A memory contains a linked list of records representative of a plurality of data transfers via a direct memory access control circuit. Each record is representative of parameters of an associated data transfer of the plurality of data transfers. The parameters of each record include a transfer start condition of the associated data transfer and a transfer end event of the associated data transfer.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 28, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: François Cloute, Sandrine Lendre
  • Method and computational tool for determining transfer functions between pairs of successive layers of a neural network
    Patent number: 11593664
    Abstract: A method can be performed prior to implementation of a neural network by a processing unit. The neural network comprising a succession of layers and at least one operator applied between at least one pair of successive layers. A computational tool generates an executable code intended to be executed by the processing unit in order to implement the neural network. The computational tool generates at least one transfer function between the at least one pair of layers taking the form of a set of pre-computed values.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 28, 2023
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.
    Inventors: Laurent Folliot, Pierre Demaj, Emanuele Plebani
  • Priority management for a transponder
    Patent number: 11595082
    Abstract: A device includes a first circuit that includes a near-field emission circuit, a second circuit, and a hardware connection linking the first circuit to the second circuit. The hardware connection is dedicated to a priority management between the first circuit and the second circuit. In addition, priority management information can be communicated between a near-field emission circuit and a second circuit. The communicating occurs between a dedicated hardware connection connecting the near-field emission circuit to the second circuit.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 28, 2023
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Detection of NFC devices
    Patent number: 11595081
    Abstract: A circuit for a communication device and a method for switching a communication device are disclosed. In an embodiment, a method includes activating at least one first antenna and at least one second antenna of a near-field communication (NFC) device for switching the NFC device between first field detection phases and second card detection phases.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 28, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Tramoni, Nicolas Cordier
  • ELECTRONIC DEVICE POWERING
    Publication number: 20230055356
    Abstract: The present disclosure relates to an electronic device comprising: at least one universal integrated circuit card or at least one secure element and at least one power supply circuit for said card or secure element, said power supply circuit being connected to at least a first power supply voltage source of the electronic device and comprising a voltage detector adapted to determine whether said first voltage source provides a first power supply voltage different from a reference voltage; and at least one near field communication module adapted to enter an active mode whenever said voltage detector determines that said first supply voltage is different from the reference voltage.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 23, 2023
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (ALPS) SAS
    Inventors: Alexandre TRAMONI, Patrick ARNOULD
  • ELECTRONIC DEVICE POWERING
    Publication number: 20230058758
    Abstract: The present disclosure relates to a method for powering an electronic device. The electronic device includes at least one universal integrated circuit card or at least one secure element; at least one power supply circuit for said card or secure element; and at least one near field communication module. When the near field communication module changes from a standby or inactive state to an active state, the following successive operations are performed: —the components and circuits of said electronic device are started; —programs of the electronic device and said secure card or element are started at the same time.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 23, 2023
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (ALPS) SAS
    Inventors: Alexandre TRAMONI, Patrick ARNOULD
  • NFC charging
    Patent number: 11588519
    Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 21, 2023
    Assignees: STMICROELECTRONICS LTD, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Chia Hao Chen, Nicolas Cordier
  • Oscillator
    Patent number: 11581880
    Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Vincent Binet, Michel Cuenca, Ludovic Girardeau
  • Integrated circuit containing a decoy structure
    Patent number: 11581270
    Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: February 14, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero