Patents Assigned to STMicroelectronics (Rousset) SAS
  • Publication number: 20220244961
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 4, 2022
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Michael PEETERS, Fabrice MARINET
  • Patent number: 11405223
    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier
  • Patent number: 11403480
    Abstract: A method for detecting an object in a housing, includes: determining a first scene inside the housing using a time of flight sensor, wherein the housing is empty during determination of the first scene; determining, by a processor, a second scene inside the housing using the time of flight sensor; comparing, by the processor, the first scene with the second scene; and determining, by the processor, a presence or an absence of the object in the housing based on a result of comparing the first scene with the second scene.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 2, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Patrick Calenzo, Sylvain Coquel, Julien Terrier, Loic Welter
  • Publication number: 20220239335
    Abstract: A method is provided that is implemented by a first NFC device configured in reader mode. The method includes evaluating an information about the coupling between the first NFC device and a second NFC device configured in card mode, as a function of the position of an antenna of the first NFC device with respect to an antenna of the second NFC device. The method further includes indicating the information by a user interface of the first device.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 28, 2022
    Applicants: STMicroelectronics Ltd, STMicroelectronics (Rousset) SAS
    Inventors: Nicolas CORDIER, Chia-Hao CHEN
  • Publication number: 20220231543
    Abstract: A contactless device includes an impedance matching and filter circuit connected to an antenna and being on the one hand operable for contactlessly communicating with a second device via the antenna, and on the other hand operable for contactlessly charging a rechargeable power supply of a third device via the antenna. A method of control includes modifying the impedance matching and filter circuit of the contactless device depending on whether the contactless device carries out the contactless communication or carries out the contactless charging.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 21, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Anthony TORNAMBE, Nicolas CORDIER
  • Patent number: 11392453
    Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 19, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Gerald Briat, Antoine De-Muynck, Alessandro Bastoni, Stephane Marmey
  • Patent number: 11393537
    Abstract: A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 19, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11387194
    Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Fabrice Marinet, Julien Delalleau
  • Patent number: 11386963
    Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 12, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11386037
    Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Emmanuel Ardichvili, Laurent Lestringand, Patrick Valdenaire
  • Patent number: 11387197
    Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 12, 2022
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Mathieu Lisart, Bruce Rae
  • Publication number: 20220214430
    Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 7, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS, STMicroelectronics Application GmbH
    Inventors: Romeo LETOR, Roberto TIZIANI, Alfio RUSSO, Antoine PAVLIN, Nadia LECCI, Manuel GAERTNER
  • Patent number: 11379238
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 5, 2022
    Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Michael Peeters, Fabrice Marinet
  • Patent number: 11381233
    Abstract: A protection circuit for a transistor switch coupled to a power supply rail operates to modulate a control voltage at a control terminal of the transistor switch. A first circuit detects an overload across the terminals of the switch with respect to a threshold to generate a signal which modulates the control voltage. A second circuit operates to adjust a value of the threshold in response to sensed variations in a supply voltage at the power supply rail.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Bienvenu, Antonio Calandra
  • Patent number: 11380377
    Abstract: A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Beatrice Brochier, Sylvain Fidelis
  • Publication number: 20220209947
    Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 30, 2022
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grand Ouest) SAS
    Inventors: Julien COUVRAND, William ORLANDO
  • Patent number: 11374569
    Abstract: The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: June 28, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Borrel, Jimmy Fort, Mathieu Lisart
  • Patent number: 11373077
    Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with different communication protocols or the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes stopping, by the contactless communication circuit, the transmission of answers of the contactless communication device to requests transmitted by a proximity coupling reader during a transaction initiated by the reader to cause the initiation by the reader of a new transaction.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 28, 2022
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Olivier Van Nieuwenhuyze, Jean-Marc Grimaud
  • Publication number: 20220194308
    Abstract: An electronic system includes at least one first electronic circuit and a voltage regulator connected electrically in parallel between first and second nodes, where the voltage regulator is configured to generate a regulated voltage at the second node. At least one second electronic circuit is connected between the second node and a third node providing a reference for the regulated voltage.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Philippe BIENVENU
  • Patent number: 11367720
    Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 21, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet