Patents Assigned to STMicroelectronics (Rousset) SAS
  • Circuit and method for detecting a fault attack
    Patent number: 10677839
    Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 9, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francesco La Rosa
  • Method for reading an EEPROM and corresponding device
    Patent number: 10675881
    Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista, Victorien Brecte
  • DOUBLE-GATE MOS TRANSISTOR WITH INCREASED BREAKDOWN VOLTAGE
    Publication number: 20200176577
    Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Julien DELALLEAU
  • Production of semiconductor regions in an electronic chip
    Patent number: 10672644
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 2, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Franck Julien
  • Electronic circuit with device for monitoring a power supply using a trip threshold chosen from a range of voltages around a band gap voltage
    Patent number: 10673431
    Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 2, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Nicolas Borrel, Francesco La Rosa
  • Pulse width modulation signal generation
    Patent number: 10664735
    Abstract: A method of reducing noise generated by pulse width modulation (PWM) signals includes generating a PWM pulse train using a first set of parameter values and modifying the PWM pulse train during a near-field communication so that the PWM pulse train is generated using a second set of parameter values. Modifying the PWM pulse train includes reducing at least one parameter value of the first set of parameter values. The method further includes resuming generation of the PWM pulse train using the first set of parameter values after the near-field communication.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 26, 2020
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Gwenael Maillet, Jean-Louis Labyre, Gilles Bas
  • METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20200160916
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Christian RIVERO
  • Pulse counting circuit
    Patent number: 10659020
    Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • Detection of a time condition relative to a two-wire bus when writing into an EEPROM on a I2C bus
    Patent number: 10649926
    Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Integrated circuit with decoupling capacitor in a structure of the triple well type
    Patent number: 10651184
    Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 12, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Device for determining the movement of a rotary element, particularly for readings of water and/or gas meters
    Patent number: 10648836
    Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: May 12, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Vincent Onde
  • Storage in a non-volatile memory
    Patent number: 10649916
    Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 12, 2020
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Michael Peeters, Fabrice Marinet, Jean-Louis Modave
  • Amplification circuit, controller, and transceiver circuit
    Patent number: 10644739
    Abstract: An amplification circuit includes a first group of amplifiers including N first amplifiers, a first terminal coupled to each output of the N first amplifiers, and a second group of amplifiers including N second amplifiers. Each of the N first amplifiers and each of the N second amplifiers includes an output. The second group of amplifiers is divided into a first subassembly of amplifiers and a second subassembly of amplifiers. The first subassembly includes M second amplifiers of the second group and the second subassembly includes N?M remaining second amplifiers of the second group. The amplification circuit further includes a second terminal and a third terminal. The second terminal is coupled to each output of the M second amplifiers and the third terminal is coupled to each output of the N?M second remaining amplifiers.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 5, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nicolas Cordier
  • METHOD FOR AUTHENTICATING A PROGRAM AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20200134164
    Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 30, 2020
    Applicants: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Vincent BERTHELOT, Layachi DAINECHE
  • Method for biasing outputs of a folded cascode stage in a comparator and corresponding comparator
    Patent number: 10630274
    Abstract: A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 21, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yohan Joly, Vincent Binet
  • SWITCHED-MODE POWER SUPPLY
    Publication number: 20200119644
    Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien ORTET, Didier DAVINO, Cedric THOMAS
  • Method for verifying the authenticity of a product
    Patent number: 10621593
    Abstract: In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then enciphered and communicated back to host device when a decision on product authenticity is made.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Denis Farison, Fabrice Romain, Christophe Laurencin
  • CIRCUIT FOR THE GENERATION OF NON-OVERLAPPING CONTROL SIGNALS
    Publication number: 20200110434
    Abstract: A signal generation circuit generates first and second non-overlapping digital signals from an input pulse signal. A first digital circuit includes: a first logical OR gate receiving the second digital signal and the input pulse signal to generate a third digital signal; and a second logical OR gate receiving the input pulse signal and a delayed version of the third digital signal to generate the first digital signal. A second digital circuit includes: a first logical AND gate receiving the first digital signal and the input pulse signal to generate a fourth digital signal; and a second logical AND gate receiving the input pulse signal and the fourth digital signal to generate the second digital signal.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 9, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Regis ROUBADIA, Ludovic GIRARDEAU
  • CONTROL OF A POWER STAGE OF A SWITCHED-MODE POWER SUPPLY
    Publication number: 20200112251
    Abstract: A driver circuit generates a drive signal having a first and second voltage state for controlling a power transistor switch coupled to a power supply node. A control circuit operates to sense a supply voltage at the power supply node and compare the sensed supply voltage to one or more voltage thresholds. In response to the comparison, the control circuit adjusts a switching slope of the drive signal from the first voltage state to the second voltage state.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 9, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Regis ROUBADIA
  • METHOD OF ACCESS TO A MEMORY
    Publication number: 20200110713
    Abstract: In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.
    Type: Application
    Filed: October 7, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Layachi DAINECHE, Xavier CHBANI, Nadia VAN-DEN-BOSSCHE