Patents Assigned to STMicroelectronics (Rousset) SAS
  • NON-VOLATILE MEMORY DATA BUS
    Publication number: 20200342930
    Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 29, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francesco LA ROSA
  • SECURE ELEMENT WITH PERSONALIZABLE FUNCTIONS AND CORRESPONDING MANAGEMENT METHOD
    Publication number: 20200341763
    Abstract: A secure element includes a non-volatile memory. The non-volatile memory stores first instructions relating to pre-established security functions and at least one second instruction relating to at least one other personalized function. A processing unit executes at least one instruction from amongst the first instructions and the at least one second instruction obtained from the non-volatile memory.
    Type: Application
    Filed: January 9, 2020
    Publication date: October 29, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Laurent TABARIES, Jean-Luc BLANC, Yveline GUILLOUX
  • EXCHANGE OF DATA WITHIN A DYNAMIC TRANSPONDER, AND CORRESPONDING TRANSPONDER
    Publication number: 20200341917
    Abstract: A first communication interface is a contactless communication interface for an integrated circuit. A second communication interface is coupled to a processing unit external to the integrated circuit. The transfer of data between the first communication interface and the second communication interface is made in a transfer mode using a volatile memory circuit. The volatile memory circuit is accessible simultaneously or virtually simultaneously firstly to processing circuit coupled to said first communication interface and secondly to said processing unit via said second communication interface.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 29, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Jose MANGIONE
  • Integrated circuit with vertically structured capacitive element, and its fabricating process
    Patent number: 10818669
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Electronic circuit
    Patent number: 10819330
    Abstract: In one embodiment, a circuit includes a plurality of elementary transistors connected in parallel between a node of application of a first potential of a power supply voltage and a node for coupling a load. The plurality of transistors includes a first assembly of elementary transistors having their gates coupled to a control node by a first circuit and a second assembly of elementary transistors having their gates coupled to the control node by a second circuit. The second circuit has two states, where the first and second circuits are configured to supply a substantially identical control voltage to the gates of the first and second assemblies of elementary transistors when the second circuit is in one of the two states.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe Bienvenu
  • Control of a power stage of a switched-mode power supply
    Patent number: 10819236
    Abstract: A driver circuit generates a drive signal having a first and second voltage state for controlling a power transistor switch coupled to a power supply node. A control circuit operates to sense a supply voltage at the power supply node and compare the sensed supply voltage to one or more voltage thresholds. In response to the comparison, the control circuit adjusts a switching slope of the drive signal from the first voltage state to the second voltage state.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 27, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Regis Roubadia
  • MOTOR CONTROL SYSTEM
    Publication number: 20200336091
    Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Gwenael MAILLET, Jean-Louis LABYRE, Gilles BAS
  • Non-oscillating comparator
    Patent number: 10812058
    Abstract: A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 20, 2020
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Vincent Binet, David Chesneau
  • DATA ENCODING ON A SERIAL BUS
    Publication number: 20200327092
    Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 15, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois TAILLIET
  • Integrated circuit with detection of thinning via the back face and decoupling capacitors
    Patent number: 10804223
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit
    Patent number: 10796992
    Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Jean-Philippe Escales
  • Transistor comprising a lengthened gate
    Patent number: 10797158
    Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Method for programming a split-gate memory cell and corresponding memory device
    Patent number: 10796763
    Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 6, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier
  • Compact non-volatile memory device of the type with charge trapping in a dielectric interface
    Patent number: 10790293
    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 29, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Method and apparatus for real-time detection of a scene
    Patent number: 10789477
    Abstract: A method for real-time detection of at least one scene by an apparatus, from among a set of possible reference scenes, includes acquiring current values of attributes from measurement values supplied by sensors. The method further includes traversing a path through a decision tree. The nodes of the decision tree are respectively associated with the attributes. The traversal considers at each node along the path, the current value of the corresponding attribute, so as to obtain at the output of the path, a scene from among the set of reference scenes. The obtained scene identifying which reference scene is the detected scene. The method further includes developing a confidence index (SC) associated with the identification of the detected scene.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 29, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pierre Demaj, Laurent Folliot
  • CO-INTEGRATION OF BULK AND SOI TRANSISTORS
    Publication number: 20200303423
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
  • Memory access control and verification using address aliasing and markers
    Patent number: 10783091
    Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 22, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Fabrice Romain
  • Method of simultaneous fabrication of SOI transistors and of transistors on bulk substrate
    Patent number: 10777552
    Abstract: The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Franck Julien
  • PROCESS FOR FABRICATING A HIGH-VOLTAGE CAPACITIVE ELEMENT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20200286986
    Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • METHOD FOR MANUFACTURING A CAPACITIVE ELEMENT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20200286896
    Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 10, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI