Patents Assigned to STMicroelectronics (Rousset) SAS
  • Controllable integrated capacitive device
    Patent number: 9721858
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 1, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Protection of an integrated circuit
    Patent number: 9716502
    Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 25, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Bruno Nicolas
  • Circuit and method for detecting a fault attack
    Patent number: 9714976
    Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: July 25, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Method for writing into and reading a multi-levels EEPROM and corresponding memory device
    Patent number: 9711230
    Abstract: During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the drain region until the cell is put into conduction. The numerical value of the item of data to be written is controlled by the level of the control voltage applied to the control gate and the item of data is de facto written with the numerical value during the putting into conduction of the cell. The programming is then stopped.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: July 18, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Protection of data stored in a volatile memory
    Patent number: 9710650
    Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Yannick Teglia
  • Method and device for transmitting information over a communication channel with variable impedance
    Patent number: 9705533
    Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 11, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Mark Wallis
  • Method for managing communication between an electronic device, for example a contactless chip card, and a communication apparatus, for example a reader, and corresponding electronic device
    Patent number: 9703996
    Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 11, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Frederic Bancel, Nathalie Link, Brigitte Hennebois, David Chomaud
  • METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT RENDERING A REVERSE ENGINEERING OF THE INTEGRATED CIRCUIT MORE DIFFICULT AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20170194267
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 6, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Dynamic sense amplifier with offset compensation
    Patent number: 9698765
    Abstract: A device includes a first and second inverters each having a signal input, signal output, high voltage supply terminal, and low voltage supply terminal. The signal input of the first inverter is coupled to the signal output of the second inverter, and the signal input of the second inverter is coupled to the signal output of the first inverter. A first transistor has a first conduction terminal coupled to a power supply node, a second conduction terminal coupled to the high voltage supply terminal of the first inverter, and a control terminal coupled to a first node. A second transistor has a first conduction terminal coupled to the power supply node, a second conduction terminal coupled to the high voltage supply terminal of the second inverter, and a control terminal coupled to a second node. First and second bit lines are capacitively coupled to the first and second nodes.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 4, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Antonino Conte
  • Method of detecting an object with a proximity sensor
    Patent number: 9689657
    Abstract: The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Maxime Teissier, Cyril Troise
  • Method of detecting an object with a proximity sensor
    Patent number: 9689659
    Abstract: The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Maxime Teissier, Cyril Troise
  • Memory cell having a vertical selection gate formed in an FDSOI substrate
    Patent number: 9691866
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH REDUCED FOOTPRINT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20170179247
    Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Method for smoothing a current consumed by an integrated circuit and corresponding device
    Patent number: 9678525
    Abstract: A method for smoothing current consumed by an electronic device is based on a series of current copying operations and on a current source delivering a reference current. The reference current is delivered in such a manner that current consumed as seen from the power supply depends on the reference current.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: June 13, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Demange, Jimmy Fort, Thierry Soude
  • Integrated circuit provided with a device for detecting its spatial orientation and/or a modification of this orientation
    Patent number: 9670058
    Abstract: An integrated circuit includes a mechanical device for detection of spatial orientation and/or of change in orientation of the integrated circuit. The device is formed in the BEOL and includes an accommodation whose sides include metal portions formed within various metallization levels. A mobile metal component is accommodated within the accommodation. A monitor inside the accommodation defines a displacement area for the metal component and includes electrically conductive elements disposed at the periphery of the displacement area. The component is configured so as to, under the action of the gravity, come into contact with the two electrically conductive elements in response to a given spatial orientation of the integrated circuit. A detector is configured to detect an electrical link passing through the component and the electrically conductive elements.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 6, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Antonio Di-Giacomo, Pascal Fornara
  • Integrated circuit protected from short circuits caused by silicide
    Patent number: 9666484
    Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 30, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Stephan Niel, Francesco La Rosa
  • STAND-BY MODE OF AN ELECTRONIC CIRCUIT
    Publication number: 20170147362
    Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.
    Type: Application
    Filed: May 12, 2016
    Publication date: May 25, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
  • Method for managing information communication between a NFC controller and a secure element within an apparatus, and corresponding apparatus and NFC controller
    Patent number: 9661448
    Abstract: A method is for managing information communication between an NFC controller coupled to an antenna for a contactless communication with an object, a device host, and a secure element. The method may include routing the information through the NFC controller, and communicating first information to be communicated between the secure element and the device host through a first communication link between the NFC controller and the device host, and through a second communication link between the NFC controller and the secure element. The method may include communicating second information with the antenna through a third communication link between the NFC controller and the secure element, the first and second communication links having bandwidths greater than a bandwidth of the third communication link.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 23, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Charles
  • DISTRIBUTION OF ELECTRONIC CIRCUIT POWER SUPPLY POTENTIALS
    Publication number: 20170141069
    Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 18, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Froidevaux, Yann Bacher
  • Metallic device having mobile element in a cavity of the BEOL of an integrated circuit
    Patent number: 9653392
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 16, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana