Patents Assigned to STMicroelectronics (Rousset) SAS
  • NFC apparatus capable to perform a contactless tag reading function
    Patent number: 9793960
    Abstract: An NFC device may include a first and second controller interfaces, a first communication channel coupled to the first controller interface, and a second communication channel connected to the second controller interface. A secure element may include a secure element interface connected to the first communication channel and encryption/decryption circuitry configured to encrypt data to be sent on the first communication channel for being framed into the encrypted frames and to decrypt encrypted data extracted from the encrypted frames and received from the first communication channel. The secure element may also include management circuitry configured to control the encryption/decryption circuitry for managing the encrypted communication with the NFC controller.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: October 17, 2017
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Application GMBH
    Inventors: Juergen Boehler, Alexandre Charles
  • Regulator for integrated circuit
    Patent number: 9787171
    Abstract: An electronic circuit includes a functional circuit in series with at least one first current source between two terminals of application of a power supply voltage. The first current source is controllable between an operating mode where it delivers a fixed current, independent from the power consumption of said functional circuit, and an operating mode where it delivers a variable current, depending on the power consumption of the functional circuit.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 10, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Jimmy Fort
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
    Patent number: 9780045
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 3, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Integrated structure comprising neighboring transistors
    Patent number: 9780098
    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 3, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Battista, François Tailliet
  • Method for writing in an EEPROM memory and corresponding device
    Patent number: 9779815
    Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 3, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Method for reading an EEPROM and corresponding device
    Patent number: 9779825
    Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 3, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista, Victorien Brecte
  • Powering of a charge with a floating node
    Patent number: 9772647
    Abstract: A circuit includes a current source series-connected with a load between first and second terminals and an element coupled in parallel with the load between the first and second terminals. A value of a current in the current source is controlled based on a current flowing in the element between the first and second terminals. The value of the current in the current source is controlled proportional to power consumption in the load based on the current flowing in the element between the first and second terminals. The element is used to limit a voltage across the load while the value of the current is being controlled.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: September 26, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Bienvenu
  • METHOD OF FORMING MOS AND BIPOLAR TRANSISTORS
    Publication number: 20170271325
    Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 21, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
  • Detection of fault injections in a random number generator
    Patent number: 9767277
    Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 19, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Reconfigurable sense amplifier for a memory device
    Patent number: 9761316
    Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 12, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Victorien Brecte
  • Non-volatile memory device having a memory size
    Patent number: 9753665
    Abstract: A memory device includes an input/output interface, a bus of SPI type coupled to the input/output interface, and a plurality of individual non-volatile memory devices connected to the bus of SPI type. The chip select inputs of each individual memory device are all connected to one and the same chip select wire of the SPI bus. The individual memory devices are further configured and controllable so as to behave, as seen by the input/output interface, as a single non-volatile memory device, the total memory space of which has a total memory capacity equal to the sum of the individual memory capacities of the individual devices.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Method of operating an integrated switchable capacitive device
    Patent number: 9754934
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Communication on an I2C bus
    Patent number: 9753886
    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • ELECTROMAGNETIC JAMMING DEVICE AND METHOD FOR AN INTEGRATED CIRCUIT
    Publication number: 20170250795
    Abstract: A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.
    Type: Application
    Filed: July 28, 2016
    Publication date: August 31, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Thomas Ordas, Alexandre Sarafianos, Stephane Chesnais, Fabrice Marinet
  • Apparatus and method for EEPROM select transistor breakdown voltage management
    Patent number: 9747053
    Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 29, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20170243652
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 24, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Phase-change memory cell having a compact structure
    Patent number: 9735353
    Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: August 15, 2017
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Simon Jeannot
  • Semiconductor structure and memory device including the structure
    Patent number: 9728248
    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 8, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Method for processing an analog signal coming from a transmission channel, in particular a signal carried by power line communications
    Patent number: 9729199
    Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 8, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mark Wallis, Yoann Bouvet, Pierre Demaj
  • Method of connecting one or more contactless components to a single antenna, and corresponding system
    Patent number: 9729202
    Abstract: A first component (CMP1) is connected to the antenna (ANT) and to an impedance matching circuit (CAI) configurable on command and connected to the antenna, and in the absence of another component (CMP2) connected to the antenna, the impedance matching circuit is placed in a first configuration in which it forms with the first component and the antenna a resonant circuit having a first resonant frequency compatible with a carrier frequency. In the presence of a second component (CMP2) connected to the antenna, the impedance matching circuit is placed in a second configuration in which it forms with the first component, the second component and the antenna a resonant circuit having a second resonant frequency compatible with the carrier frequency.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 8, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Tramoni, Pierre Rizzo