Patents Assigned to STMicroelectronics (Rousset) SAS
  • Individually read-accessible twin memory cells
    Patent number: 9653470
    Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Electronic switching device with reduction of leakage currents and corresponding control method
    Patent number: 9654095
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Single wire bus communication protocol
    Patent number: 9639500
    Abstract: A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Gilles Bas, Hervé Chalopin, François Tailliet
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
    Patent number: 9640493
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Measurement of variations of a power supply voltage
    Patent number: 9638728
    Abstract: A circuit has a supply line, a reference line and circuitry coupled between the supply line and the reference line. The circuitry outputs a regulated voltage and a measurement voltage. An analog-to-digital converter (ADC) generates a digital signal indicative of variations of potential differences between the supply line and the reference line based on the regulated voltage and the measurement voltage. The generated digital signal may be used to control the circuit.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 2, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yann Bacher, Nicolas Froidevaux
  • Anticollision mechanism for an NFC device
    Patent number: 9634725
    Abstract: A device includes near-field communication (NFC) control circuitry and transceiver circuitry. The transceiver circuitry is coupled to the NFC control circuitry. In a reader mode of operation, the NFC circuitry detects reception of NFC polling frames by the transceiver circuitry. When reception of an NFC polling frame is detected, the NFC control circuitry switches from the reader mode of operation to a card mode of operation.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: April 25, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Rizzo, Nathalie Vallespin, Emmanuel Papart
  • Method for estimating a time invariant transmission channel, and corresponding receiver
    Patent number: 9628144
    Abstract: A method is for processing an analog channel signal from a transmission channel. The method may include converting of the analog channel signal to a digital channel signal, and performing a channel estimation digital processing of the digital channel signal. The channel estimation digital processing may include for at least one frame, generating transfer functions of the transmission channel, the transfer functions respectively associated with reference symbols of the frame, and averaging processing of the transfer functions to generate an average transfer function. The method may include decoding of symbols of the frame following the reference symbols using the average transfer function.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 18, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Demaj, Yoann Bouvet
  • Sense amplifier circuit with offset compensation for a non-volatile memory device
    Patent number: 9627011
    Abstract: A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.
    Type: Grant
    Filed: July 16, 2016
    Date of Patent: April 18, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Antonino Conte, Francesco La Rosa
  • Protection of a radio frequency transmit-receive terminal against electromagnetic disturbances
    Patent number: 9626614
    Abstract: An antenna circuit for a device of transmission/reception by inductive coupling, including a first inductive element in parallel with a capacitive element and, between each node of the parallel association and two terminals of a switch, a second inductive element.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: April 18, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Data access in a mobile device with NFC
    Patent number: 9628146
    Abstract: The disclosure concerns an NFC (near field communications) device having an NFC router. The NFC router includes a memory adapted to store data to be shared with an external device and an NFC antenna circuit. The NFC router is capable of operating in a card emulation mode in which the shared data stored by the memory is accessible via the NFC antenna circuit.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 18, 2017
    Assignees: Proton World International N.V., STMicroelectronic (Rousset) SAS
    Inventors: Olivier Van Nieuwenhuyze, Alexandre Charles
  • Twin memory cell interconnection structure
    Patent number: 9627068
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
    Publication number: 20170098615
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Application
    Filed: April 25, 2016
    Publication date: April 6, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Dual non-volatile memory cell comprising an erase transistor
    Patent number: 9613709
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 4, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Detection of fault injections in a random number generator
    Patent number: 9582664
    Abstract: A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 28, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Compact memory device of the EEPROM type with a vertical select transistor
    Patent number: 9583193
    Abstract: Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 28, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Zener diode having an adjustable low breakdown voltage
    Patent number: 9577116
    Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • Method and system for managing a writing cycle of a data in a EEPROM memory cell
    Patent number: 9576670
    Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 21, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Zener diode having an adjustable breakdown voltage
    Patent number: 9577053
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • Vertical bipolar transistor
    Patent number: 9570513
    Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: February 14, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Francesco La Rosa, Julien Delalleau
  • Protection of a non-volatile memory by change of instructions
    Patent number: 9563787
    Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 7, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia