Patents Assigned to STMicroelectronics (Rousset) SAS
  • Method for biasing an embedded source plane of a non-volatile memory having vertical select gates
    Patent number: 9368215
    Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: June 14, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Power management in an electromagnetic transponder
    Patent number: 9367784
    Abstract: An electromagnetic transponder includes an oscillatory circuit, a battery and a first rectifier bridge. Alternating current input terminals of the rectifier bridge are connected to the terminals of the oscillatory circuit, and at least two rectifier elements of the rectifier bridge are controllable on the basis of the voltage supplied by the battery.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: June 14, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Cryptographic countermeasure method by deriving a secret data
    Patent number: 9363073
    Abstract: A method of protecting a circuit from attacks aiming to discover secret data used during the execution of a cryptographic calculation by the circuit, by, executing a transformation calculation implementing a bijective transformation function, receiving as input a secret data, and supplying a transformed data, executing a cryptographic calculation receiving as input a data to process and the transformed data, and executing an inverse transformation calculation receiving as input the result of the cryptographic calculation, and supplying a result that the cryptographic calculation would have supplied if it had been applied to the data to process and directly to the secret data, the data to process belong to a stream of a multiplicity of data, the transformed data being supplied as input to the cryptographic calculation for all the data of the stream.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: June 7, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Voltage and power limiter for an electromagnetic transponder
    Patent number: 9361489
    Abstract: An electromagnetic transponder including a resonant circuit; a rectifying bridge having input terminals connected across the resonant circuit and having rectified output terminals providing an electronic circuit power supply voltage; and a device for limiting the voltage across the resonant circuit, connected between the input terminals of the rectifying bridge.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: June 7, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Marc Battista, Gilles Bas, Francois Tailliet
  • Electrically controllable integrated switch
    Patent number: 9355802
    Abstract: An integrated circuit includes an interconnection part with several metallization levels. An electrically activatable switching device within the interconnection part has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 31, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • Assistance for positioning a transponder
    Patent number: 9356656
    Abstract: A method for assisting with positioning of an electromagnetic transponder by a user with respect to a terminal, wherein: a first value of the current in an oscillating circuit of the terminal is periodically measured; a second value of a ratio between a no-load value of this current, stored when no transponder is in the field of the terminal, and the first value, is calculated; and pieces of information intended for the user are controlled according to said second value.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 31, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Luc Wuidart
  • Secure NFC routing
    Patent number: 9351164
    Abstract: A processing device of an NFC device receives a request, initiated by a first application loaded in a memory of the NFC device, to modify one or more parameters of an NFC routing table of an NFC router of the NFC device. The NFC routing table has parameters indicating the devices to which NFC messages are to be routed. The processing device retrieves a first identifier associated with the application and transmits the first identifier to the NFC router. The NFC router, based on the first identifier, verifies whether or not the application is authorized to modify the routing table.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 24, 2016
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Olivier Van Nieuwenhuyze, Christophe Henri Ricard
  • EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS
    Publication number: 20160141032
    Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 19, 2016
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • Protection of communication by an electromagnetic transponder
    Patent number: 9344156
    Abstract: A method for protecting communication between an electromagnetic transponder and a terminal, wherein the transmission of an acknowledgement for a request received from a terminal by the transponder is only allowed when the transponder is in mechanical contact or in quasi-mechanical contact with the terminal.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 17, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Luc Wuidart
  • Writing into an EEPROM on an I2C bus
    Patent number: 9343157
    Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 17, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • DEVICE FOR DETECTING A LASER ATTACK IN AN INTEGRATED CIRCUIT CHIP
    Publication number: 20160133582
    Abstract: A device for detecting a laser attack made on an integrated circuit chip comprises a bipolar transistor of a first type formed in a semiconductor substrate, that bipolar transistor comprising a parasitic bipolar transistor of a second type. A buried region, forming the base of the parasitic bipolar transistor, operates as a detector of the variations in current flowing caused by impingement of laser light on the substrate.
    Type: Application
    Filed: April 15, 2015
    Publication date: May 12, 2016
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabrice Marinet, Julien Mercier, Jimmy Fort, Alexandre Sarafianos
  • Method for detecting electrical energy produced from a thermoelectric material contained in an integrated circuit
    Patent number: 9331027
    Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: May 3, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Countermeasure method and device for protecting data circulating in an electronic component
    Patent number: 9331847
    Abstract: The disclosure relates to a countermeasure method in an electronic component, wherein binary data are transmitted between binary data storage units, binary data being transmitted in several transmission cycles comprising a first cycle comprising: randomly selecting bits of the data, transmitting the selected bits and transmitting bits, each having a randomly chosen value, instead of transmitting non-selected bits of the data. A last transmission cycle comprises transmitting bits of the data that have not been transmitted during a previous cycle.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 3, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Frédéric Bancel
  • Method of making an integrated switchable capacitive device
    Patent number: 9324706
    Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Secure method for processing a content stored within a component, and corresponding component
    Patent number: 9323941
    Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Mathieu Lisart
  • Method and device for managing the time transition of a CMOS logic circuit as a function of temperature
    Patent number: 9325325
    Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Protection of a non-volatile memory by change of instructions
    Patent number: 9311510
    Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: April 12, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Method and device for fault detection
    Patent number: 9311477
    Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 12, 2016
    Assignees: Proton World International N.V., STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Jean-Louis Modave, Gilles Van Assche, Ronny Van Keer
  • EEPROM programming with first and second programming modes
    Patent number: 9312012
    Abstract: A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: April 12, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES
    Publication number: 20160093696
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero