Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: An adjustable bandgap reference voltage includes a first circuit for generating IPTAT, a second circuit for generating ICTAT, and an output module configured to generate the reference voltage. The first circuit includes a first amplifier connected to terminals of a core for equalizing voltages across the terminals, where the first amplifier has a first stage that is biased by the current inversely proportional to absolute temperature and is arranged according to a folded setup with first PMOS transistors arranged according to a common-gate setup. The first circuit also includes a feedback stage with an input connected to the first amplifier output. The feedback stage output is connected to the first stage input and to a terminal of the core. The second circuit includes a follower amplifier connected to a terminal of the core and separated from the first amplifier and the output module is connected to the feedback stage.

Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes for which the access to the areas is authorized or forbidden is associated with each of these areas.

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

Abstract: A method for configuring a first device for a near-field communication with a second device, wherein a peer-to-peer mode is selected if the second device draws the power supply of its circuits from a battery.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.

Abstract: An electronic circuit including two ring oscillators, wherein the output of each ring oscillator is looped back on the input of this same oscillator as well on the input of the other oscillator. The application of such a circuit to the detection of a dynamic disturbance.

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.

Abstract: A method for protecting a security module equipping a telecommunication device equipped with a near-field communication router, against an attempt of diversion of a communication channel between a gate of this security module and a gate of the router, wherein, for each request from the router to the security module, the module verifies the rights of access to the information that is contains according to the origin of the request.

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract: A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules.

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract: A circuit includes a current source intended to be series-connected with a load between two terminals of application of a first D.C. voltage. An element limits the voltage across the load and a circuit controls the value of the current in the current source with the current flowing in the element.

Abstract: An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device.