Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Non-volatile memory for NFC router
    Patent number: 9214986
    Abstract: A plurality of circuits in a same package including a first integrated circuit having at least one NFC-type communication interface and at least one communication interface of another type, and a second integrated circuit having a security module with a non-volatile memory, the non-volatile memory being used by the NFC interface to store configuration data.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 15, 2015
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Charles
  • Method of checking the matching of an antenna connected to a NFC component and corresponding NFC component
    Patent number: 9209516
    Abstract: An NFC component includes a first interface that can be used in reader mode and is configured to be connected to an antenna via an impedance matching external circuit. A second interface can be used in card mode and in reader mode and is configured to be connected to the antenna and to the first interface via the impedance matching external circuit. An internal module includes a first detection circuit configured to deliver a first detection signal that represents the phase antenna matching quality when the impedance matching external circuit and the antenna are indeed connected between the first interface and the second interface. The internal module is further configured to deliver a check signal from at least the first detection signal.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 8, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Alexandre Tramoni
  • Mechanism for writing into an EEPROM on an I2C bus
    Patent number: 9202568
    Abstract: A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: December 1, 2015
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH AN ACTIVE REGION UNDER RELAXED COMPRESSIVE STRESS, AND ASSOCIATED DECOUPLING CAPACITOR
    Publication number: 20150340426
    Abstract: An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 26, 2015
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Sylvie Wuidart, Christian Rivero, Guilhem Bouton, Pascal Fornara
  • Method of fabricating a vertical MOS transistor
    Patent number: 9196654
    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 24, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Perforated electronic package and method of fabrication
    Patent number: 9196590
    Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 24, 2015
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Francis Steffen, Delphine Mathey, Gilbert Assaud, Rémi Brechignac
  • Regulator with low dropout voltage and improved stability
    Patent number: 9190969
    Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 17, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Thierry Soude
  • Integrated thermoelectric generator
    Patent number: 9177994
    Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 3, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Protection of a security element coupled to an NFC circuit
    Patent number: 9179307
    Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 3, 2015
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Charles
  • Protection of a non-volatile memory by change of instructions
    Patent number: 9165165
    Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 20, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • EEPROM cell with charge loss
    Patent number: 9165775
    Abstract: An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 20, 2015
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Pascal Fornara
  • Method for block-erasing a page-erasable EEPROM-type memory
    Patent number: 9159430
    Abstract: A method for erasing a page-erasable EEPROM-type memory includes: the memory receiving a command associated with a set of addresses of pages of the memory to be erased, each page comprising several memory cell groups each forming a word, for each address of the set of addresses, selecting a word line corresponding to a page of the memory, and triggering the simultaneous erasing of all the selected word lines.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: October 13, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Method for processing transmission errors, in particular noise, during a contactless communication between a card and a reader
    Patent number: 9146806
    Abstract: A method is for processing transmission errors during contactless communication of information between a device and a reader. The information may be transmitted in the form of frames sent to a send/receive module of the reader in contactless coupling with the device and controlled by a control module coupled to the send/receive module. The information may be extracted from the frames within the send/receive module so as to be delivered to the control module. The method may include a detection of transmission errors that are to be ignored.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 29, 2015
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, MELEXIS TECHNOLOGIES SA
    Inventors: Thierry Bousquet, Oleksandr Zhuk
  • Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
    Patent number: 9142951
    Abstract: Disclosed herein is a device comprising a protection circuit configured to protect against a polarity reversal of the input DC power supply voltage, the protection circuit comprising an N-channel main transistor having a source coupled to an input terminal and having a drain coupled to an output terminal, a command circuit configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and a control circuit configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: September 22, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Antoine Pavlin
  • PERFORATED ELECTRONIC PACKAGE AND METHOD OF FABRICATION
    Publication number: 20150262941
    Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 17, 2015
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Francis Steffen, Delphine Mathey, Gilbert Assaud, Rémi Brechignac
  • COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD
    Publication number: 20150255540
    Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 10, 2015
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Method of compensating for effects of mechanical stresses in a microcircuit
    Patent number: 9127994
    Abstract: A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 8, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES
    Publication number: 20150249132
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: February 20, 2015
    Publication date: September 3, 2015
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara
  • Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device
    Patent number: 9123413
    Abstract: A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 1, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Device for detecting the thinning down of the substrate of an integrated circuit chip
    Patent number: 9121896
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: September 1, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero