Abstract: A method for recording at least one block of variable data in a first volatile memory external to a microprocessor, including calculating and storing a digital signature taking into account at least partially the address and the content of said data block in the memory, and at least a first random digital value internal to the microprocessor.

Abstract: A device and a method of deinterlacing a sequence of images from an interlaced format to a progressive format. The sequence of images being composed of successive frames. A plurality of pixels of missing lines of a current frame to be completed, an evaluation of the values of these pixels according to a spatially consistent order. The evaluation comprises, for each pixel of the plurality of pixels, estimating a direction of interpolation, spatial interpolation according to the estimated direction of interpolation. According to the invention, the estimation step comprises, for at least one current pixel of the plurality of pixels, calculating a score for at least two directions, and selecting the direction of interpolation on the basis of the calculated scores and of the estimated direction of interpolation for a distinct pixel situated in the neighborhood of the current pixel.

Abstract: A switched-mode power converter, including, between a first end of a main inductive element and a switch, a two-value inductive element automatically switching between its two values.

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing of data from the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract: A power management unit for a battery-operated electronic device having a bus interface for the interconnection with another electronic device, the power management unit including an electric energy storage element coupled between a battery of the battery-operated electronic device and a voltage supply line of the bus interface, the electric energy storage element being operable to charge/discharge electric energy; a drive circuitry arranged to control a charge/discharge of the electric energy storage element. The drive circuitry is operable to cause an electric power supplied by the other electronic device through the voltage supply line to re-charge the battery; or, in case the other electronic device does not supply electric power, cause the battery supply electric power to the other electronic device through the voltage supply line. The power management unit is particularly adapted for battery-operated, mobile USB OTG devices.

Abstract: A method for protecting the execution of an algorithmic calculation taking into account at least one valid piece of data and at least one secret key by an integrated circuit, and performing several iterations of an encryption calculation, including executing the algorithm with the valid data between several executions of the same algorithm with invalid data corresponding to a combination of the valid data with predetermined masks.

Abstract: An image capture device includes n image sensors arranged to capture images respectively of a same scene according to at least three different colors, each of the sensors comprising a pixel array, each pixel being associated with a MOS transfer transistor, the transfer transistors of n neighboring pixels being associated with a same output; and a read circuit associated with control circuitry for reading separately, the output of each transfer transistor, or cumulatively, the outputs of from two to n neighboring transfer transistors.

Abstract: A device for suppressing pulse interferences contained in a signal, including a circuit for detecting pulse interferences contained in the signal, and a circuit for correcting the signal disturbed by the detected pulse interferences, in which the detection circuit comprises a circuit for determining a first coefficient representative of a statistical feature of the variation of the signal over a first time period; a circuit for determining a second coefficient representative of a statistical feature of the variation of the signal over a second time period longer than the first time period; and a comparison circuit comparing the first and second coefficients and providing a signal indicative of the presence of a pulse interference over the first time period when the first coefficient clearly differs from the second coefficient.

Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Abstract: A method for regulating the biasing voltage of column control circuits of an array screen formed of LEDs distributed in lines and columns, the column control circuits being adapted to turning on at least one LED of a line. The method includes increasing the biasing voltage when the current flowing through at least one activated LED is smaller than a determined luminance current and of decreasing the biasing voltage when the current flowing through each activated LED is equal to the determined luminance current.

Abstract: A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.

Abstract: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Abstract: An integrated circuit including a structure of inductances on a semiconductor substrate, intended for operating at frequencies greater than several hundreds of MHz, including a first inductance formed by a conductive track and having first and second terminals respectively connected to each of the two ends of the conductive track, including a second inductance formed by the conductive track between the second terminal and any intermediary point of the conductive track connected to a third terminal, said second and third terminals forming the two terminals of the second inductance, and means for setting the third terminal to high impedance when the first inductance is used.

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract: An image capture device includes first and second image sensors arranged to capture first and second images respectively of a same scene, each of the first and second images including pixel values; an objective lens associated with each of the image sensors, one objective lens being axially offset with respect to the other and having the same focal length as the other; a unit for analyzing the sharpness of each image; and a unit for selecting the image of desired sharpness.

Abstract: A method and a circuit for standardizing a noise source providing an initial bit flow, including dividing the initial bit flow into bit words of identical lengths, and assigning an output state according to the states of the bits of the current word and to a pre-established assignment rule, the assignment rule being inverted according to the occurrence, in the initial bit flow, of words, all the bits of which have identical states.

Abstract: A circuit for protecting electronic equipment intended to be connected to at least one first conductor of a communication line, including, between this first conductor and a second conductor of the line or the ground to which is connected the equipment to be protected, at least one first branch including, in series, a first capacitive element and a first voltage-threshold triggering element, a first resistive element being connected in parallel with the first capacitive element.

Abstract: A method and a system of access control between a main processor and peripherals connected by a communication bus, including assigning, to all or part of the programs to be executed by the main processor, at least one token selectively authorizing access to one or several of said peripherals, said token being provided at least initially by an auxiliary processor exploiting a memory distinct from that of the main processor; and checking, for each request of access of one of said programs to one of said peripherals, the presence of said authorization token for the access to the concerned peripheral.